DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 04/07/2026. Claims 3, 7-20, 22, 25, 26, 29, 34 have been cancelled. Claims 38-40 are new. Claims 1, 2, 4-6, 21, 23, 24, 27, 28, 30-33 and 35-40 are pending in the Application, of which Claims 1, 23 and 30 are independent.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/07/2026 has been entered.
Continuity/ Priority Information
The present Application 18778993 filed 07/21/2024 is a Divisional of 17724963, filed 04/20/2022, now U.S. Patent No. 12,431,214 and Claims Priority from Provisional Application 63294527, filed 12/29/2021.
Response to Arguments
Applicant's arguments filed 04/07/2026, with respect to the rejection of Claims under 35 U.S.C. 102(a)(1) as being anticipated by Boeve (Pub. No. US 20080279027) have been fully considered but they are not persuasive, as set forth in the present office action.
Applicant argues that Boeve does not disclose “determining that the memory data read from the MRAM device cannot be corrected using the error correction redundancy bits in response to determining that the retention failure rate is greater than the failure rate threshold”, as recited in amended independent claim 1.
As best understood, Boeve fails to disclose that the error correction redundancy bits cannot correct the memory data, when the retention failure rate is greater than a threshold.
In response to Applicant arguments, Boeve disclose para. [0020] Another detection of degradation may be based on e.g. the data. When an excessive amount of errors is detected in the data that may be encoded, it may be concluded that the reference signal may be degraded, i.e. the "memory data is untrustworthy". Hence, degradation may be detected by determining abnormal levels of data errors by means of for example a data error detection and correction system of a non-volatile memory device.
Clearly, when an excessive amount of errors is detected in the data, the memory device becomes uncorrectable, and therefore as it is well known in the art, a data error detection and correction system is not capable of correcting the data due to abnormal levels of errors in the memory.
For example, the specification describes, para. [0030] At act 208, in some embodiments, if the data retention failure rate is smaller than, or no greater than, the failure rate threshold as determined by act 206, an error correction operation can be performed to correct the error bits. Para. [0031] At act 210, in some embodiments, a notification signal is provided if the data retention failure rate is greater, or no smaller, than the failure rate threshold as determined by act 204. The data retention failure rate exceeding the failure rate threshold may indicate a strong external magnetic field around the MRAM device, and that the stored memory data is untrustworthy, i.e. memory device becomes uncorrectable.
Furthermore, there is nowhere in the original specification that describes that the error correction redundancy bits cannot correct the memory data, when the retention failure rate is greater than a threshold.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 2, 4-6, 21, 23, 24, 27, 28, 30-33 and 35-40 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 23 and 30, “determining that the memory data read from the MRAM device cannot be corrected using the error correction redundancy bits….” is a new mater, which was not described in the specification as originally filed.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 4-6, 21, 23, 24, 27, 28, 30-33 and 35-40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 23 and 30, recite a negative limitation “determining that the memory data read from the MRAM device cannot be corrected using the error correction redundancy bits….”, which render the Claims indefinite, i.e. due to the inclusion of expression “device cannot be corrected”. It is not clear how one of ordinary skill in the art is unable correct a memory device using error correction redundancy. The limitations as recited, tend to define the invention in terms of what it is not, rather than pointing out the invention. Any negative limitation or exclusionary proviso must have basis in the original disclosure. In this case, there is no sufficient description in the specification for the negative limitation.
Applicant should recite limitations from the specification into the Claims “by enabling a special interface and sending a dedicated read command” to access the verification portion.
Any claims not specifically mentioned above are rejected because of their dependency on a rejected claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4-6, 21, 23, 24, 27, 28, 30-33 and 35-40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Boeve (Pub. No. US 20080279027) Pub. Date: 2008-11-13.
Regarding independent Claims 1, 23 and 30, Boeve discloses non-volatile memory devices, MRAMs, systems containing such memory devices, and methods of operating such devices, comprising:
reading memory data and error correction redundancy corresponding to the memory data from the MRAM device; determining a bit error rate by executing error correction code (ECC) check based on the memory data and the error correction redundancy, the bit error rate indicating a retention failure rate of the MRAM device; FIG. 2, [0058] The NVM device 10 according to the present invention comprises a number of memory cells 20, a reference cell or cells 30 and read circuitry 40. The reference cell or cells 30 output a reference signal or signals to the read circuitry 40 for use in deciding or determining a data value of raw data output by or extracted from the memory cells 20. Deciding or determining a data value of raw data output may be performed by determining which data value from a limited set of data values, e.g. from the set of binary values 0, 1, is represented by the memory cell 20. Therefore, a threshold detection can be performed during read operation. The output of the memory cell 20 is in fact compared to a reference value.
[0059] Degradation in the reference signal is detected by a reference degrade detector 50. Data values decided or determined by the comparison of the raw data with the reference signal, typically binary values, are output to a data error detection and correction part 60. The corrected data values are output to the processor and other parts of the system 70. The read circuitry 40 causes a read operation by addressing the memory cells 20 according to established practice, which need not be described here in more detail.
comparing the retention failure rate with a failure rate threshold that is pre- determined; and determining that the memory data read from the MRAM device cannot be corrected using the error correction redundancy bits in response to determining that the retention failure rate is greater than the failure rate threshold; providing a notification signal indicating that the memory data is untrustworthy if the retention failure rate is greater than the failure rate threshold. [0020] Another detection of degradation may be based on e.g. the data. When an excessive amount of errors is detected in the data that may be encoded, it may be concluded that the reference signal may be degraded corresponding to “memory data is untrustworthy”. Hence, degradation may be detected by determining abnormal levels of data errors by means of for example a data error detection and correction system of a non-volatile memory device.
wiping the memory data by overwriting the memory data with meaningless data, different than the memory data, in response to the retention failure rate being greater than the failure rate threshold.
In light of the 112b rejection, the limitation is interpreted as “wiping out the memory data by rewriting the memory data” consistent with the specification. Boeve, [0026] The device according to the present invention may furthermore comprise a reference rewrite means or circuit for rewriting the reference cell if it is determined to be degraded. [0063] FIG. 3, If an error, such as for example a value outside of the normal range, is detected by the test cell error detector 160, the error detector 160 will output a trigger signal to a reference rewrite circuit 170. Such errors may, for example, be caused by thermal instability.
Regarding Claims 2, 4, 6, Boeve discloses performing an error correction operation and rewriting the MRAM device with corrected bits of the memory data if the retention failure rate is smaller than the failure rate threshold. [0059] Data values decided or determined by the comparison of the raw data with the reference signal, typically binary values, are output to a data error detection and correction part 60. The corrected data values are output to the processor and other parts of the system 70.
Regarding Claims 5, 21, 24, 27, Boeve discloses determining a strength of an external magnetic field around the MRAM device; [0068] FIG. 5 also shows two currents I.sub.1 and I.sub.2 that can be used for generating the local magnetic field components H.sub.1 and H.sub.2 required for performing a programming operation on the reference elements 220. One of these components, i.e. H.sub.1, is shared along a column of reference elements 220. The other, i.e. H.sub.2, is shared across a row including one of the reference elements 220 and a memory element 210 from each of the columns of memory elements 210.
[0069] FIG. 6 shows a graph of the H.sub.1 component as a function of the H.sub.2 component of the generated effective magnetic field for the reference elements 220. The curve on the graph shows a minimum amount of each of the effective magnetic field components to give a sufficient effective magnetic field for writing. The dotted line represents the line of points where the two components are equal.
Regarding Claim 28, Boeve discloses the ECC check determines a bit error rate of the memory data stored in the MTJ array; [0059] Degradation in the reference signal is detected by a reference degrade detector 50. Data values decided or determined by the comparison of the raw data with the reference signal, typically binary values, are output to a data error detection and correction part 60. The corrected data values are output to the processor and other parts of the system 70.
[0076] When a substantial amount of `errors` is being detected, e.g. in which way and how frequently the error correction schemes had to be applied, this can then be followed by re-writing the reference elements 220, after which data can be re-read. The amount of errors should be substantially reduced, if the problem had to do with the stability of the reference cells 130. This may also be implemented when memory elements 210 and reference elements 220 are identical.
Regarding Claim 35, control when the fatal external magnetic field is applied to the MTJ array and is removed from the MTJ array; [0069] FIG. 6 shows a graph of the H.sub.1 component as a function of the H.sub.2 component of the generated effective magnetic field for the reference elements 220. The curve on the graph shows a minimum amount of each of the effective magnetic field components to give a sufficient effective magnetic field for writing. The dotted line represents the line of points where the two components are equal.
Regarding Claims 36, 37, Boeve discloses correct the memory data by overwriting the memory data with corrected memory data; and determine at what strength the magnetic field the data is uncorrectable. [0063] FIG. 3. Also shown is a detector 180 for detecting an abnormal level of data errors “data is uncorrectable” based on the read data values output by a data error detection and correction part 60. The data detection and/or correction may be carried out using a number of conventional techniques which are known by a skilled person and hence, do not need to be described here in more detail.
Regarding Claims 38-40, Boeve discloses determine the strength of the external magnetic field around the MTJ array to be a first strength based on the data retention failure rate being a first rate; and determine the strength of the external magnetic field around the MTJ array to be a second strength, greater than the first strength, in response to the data retention failure rate being a second rate greater than the first rate.
[0068] FIG. 5 also shows two currents I.sub.1 and I.sub.2 that can be used for generating the local magnetic field components H.sub.1 and H.sub.2 required for performing a programming operation on the reference elements 220. One of these components, i.e. H.sub.1, is shared along a column of reference elements 220. The other, i.e. H.sub.2, is shared across a row including one of the reference elements 220 and a memory element 210 from each of the columns of memory elements 210.
[0069] FIG. 6 shows a graph of the H.sub.1 component as a function of the H.sub.2 component of the generated effective magnetic field for the reference elements 220. The curve on the graph shows a minimum amount of each of the effective magnetic field components to give a sufficient effective magnetic field for writing. The dotted line represents the line of points where the two components are equal.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
US 12,321,263 Houssameddine; Dimitri et al. FIG. 8 is a flowchart diagram, generally designated 800, for determining whether to increase the error correction code strength for correcting bit errors in an MRAM chip in accordance with at least one embodiment of the present invention.
US 20200104205 Noguchi; Hiroki et al. [0041] The output of the GF multi calculation circuit 356 is input into the error correction circuit 362 along with the readout data and syndrome s1. The output of the error correction circuit 362 is the error-corrected codeword. The check bit generator 353 then operates on the corrected word, e.g. the data without the parity bits, encodes parity bits according to the predefined parity-check matrix of the chosen ECC type or scheme, forming the corrected codeword to be written to the local memory array 102a.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: April 27, 2026
Non-Final Rejection 20260427
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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