DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 01/09/2026. Claims 3, 7-20, 29, and 34 have been cancelled. Claims 35-37 are new.
Claims 1, 2, 4-6, 21-28, 30-33, and 35-37 are pending in the Application, of which Claims 1, 23 and 30 are independent.
Continuity/ Priority Information
The present Application 18778993 filed 07/21/2024 is a Divisional of 17724963, filed 04/20/2022, now U.S. Patent No. 12,431,214 and Claims Priority from Provisional Application 63294527, filed 12/29/2021.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 4-6, 21, 22, 36, 25, 32, 36, are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 25, 32, 36, “wiping the memory data by overwriting the memory data with meaningless data, different than the memory data” is indefinite. There is no sufficient support in the specification for the expression “overwriting the memory data with meaningless data”.
According to the specification para. [0023], when the number or scale of the error bits exceeds a pre-determined threshold, a further action may also be taken according to the acquired number or scale of the error bits, such as wiping out the memory data for security purpose and/or rewriting the memory data.
However, there is no further explanation of how to wipe out the memory, other than rewriting the memory data. Therefore, the limitation is interpreted as “wiping out the memory data by rewriting the memory data”.
Any claim not specifically mentioned above is rejected because of its dependency on a rejected claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4-6, 21-28, 30-33, and 35-37 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Boeve (Pub. No. US 20080279027) Pub. Date: 2008-11-13.
Regarding independent Claims 1, 23 and 30, Boeve discloses non-volatile memory devices, MRAMs, systems containing such memory devices, and methods of operating such devices, comprising:
reading memory data and error correction redundancy corresponding to the memory data from the MRAM device; determining a bit error rate by executing error correction code (ECC) check based on the memory data and the error correction redundancy, the bit error rate indicating a retention failure rate of the MRAM device; FIG. 2, [0058] The NVM device 10 according to the present invention comprises a number of memory cells 20, a reference cell or cells 30 and read circuitry 40. The reference cell or cells 30 output a reference signal or signals to the read circuitry 40 for use in deciding or determining a data value of raw data output by or extracted from the memory cells 20. Deciding or determining a data value of raw data output may be performed by determining which data value from a limited set of data values, e.g. from the set of binary values 0, 1, is represented by the memory cell 20. Therefore, a threshold detection can be performed during read operation. The output of the memory cell 20 is in fact compared to a reference value.
[0059] Degradation in the reference signal is detected by a reference degrade detector 50. Data values decided or determined by the comparison of the raw data with the reference signal, typically binary values, are output to a data error detection and correction part 60. The corrected data values are output to the processor and other parts of the system 70. The read circuitry 40 causes a read operation by addressing the memory cells 20 according to established practice, which need not be described here in more detail.
comparing the retention failure rate with a failure rate threshold that is pre- determined; and providing a notification signal indicating that the memory data is untrustworthy if the retention failure rate is greater than the failure rate threshold. [0020] Another detection of degradation may be based on e.g. the data. When an excessive amount of errors is detected in the data that may be encoded, it may be concluded that the reference signal may be degraded corresponding to “memory data is untrustworthy”. Hence, degradation may be detected by determining abnormal levels of data errors by means of for example a data error detection and correction system of a non-volatile memory device.
wiping the memory data by overwriting the memory data with meaningless data, different than the memory data, in response to the retention failure rate being greater than the failure rate threshold.
In light of the 112b rejection, the limitation is interpreted as “wiping out the memory data by rewriting the memory data” consistent with the specification. Boeve, [0026] The device according to the present invention may furthermore comprise a reference rewrite means or circuit for rewriting the reference cell if it is determined to be degraded. [0063] FIG. 3, If an error, such as for example a value outside of the normal range, is detected by the test cell error detector 160, the error detector 160 will output a trigger signal to a reference rewrite circuit 170. Such errors may, for example, be caused by thermal instability.
Regarding Claims 2, 4, 6, Boeve discloses performing an error correction operation and rewriting the MRAM device with corrected bits of the memory data if the retention failure rate is smaller than the failure rate threshold. [0059] Data values decided or determined by the comparison of the raw data with the reference signal, typically binary values, are output to a data error detection and correction part 60. The corrected data values are output to the processor and other parts of the system 70.
Regarding Claims 5, 21, 22, 24, 27, Boeve discloses determining a strength of an external magnetic field around the MRAM device; [0068] FIG. 5 also shows two currents I.sub.1 and I.sub.2 that can be used for generating the local magnetic field components H.sub.1 and H.sub.2 required for performing a programming operation on the reference elements 220. One of these components, i.e. H.sub.1, is shared along a column of reference elements 220. The other, i.e. H.sub.2, is shared across a row including one of the reference elements 220 and a memory element 210 from each of the columns of memory elements 210.
[0069] FIG. 6 shows a graph of the H.sub.1 component as a function of the H.sub.2 component of the generated effective magnetic field for the reference elements 220. The curve on the graph shows a minimum amount of each of the effective magnetic field components to give a sufficient effective magnetic field for writing. The dotted line represents the line of points where the two components are equal.
Regarding Claims 25, 26, Boeve discloses controller is configured to write refreshed memory data to the MTJ array; [0072] Also, the write operation may be changed specifically for the reference elements. In conventional MRAM, it is for example possible to deviate from the 45 degree write angle, which would be giving the lowest effective magnetic field needed for writing. From a more complex analysis, it is possible to deduce that the darker triangle area in FIG. 6 represents the field window for reliable write operations in a memory array, combining reliable write operation on the selected magnetic element and sufficient stability for other magnetic elements on the same write lines against half-selects.
Regarding Claim 28, Boeve discloses the ECC check determines a bit error rate of the memory data stored in the MTJ array; [0059] Degradation in the reference signal is detected by a reference degrade detector 50. Data values decided or determined by the comparison of the raw data with the reference signal, typically binary values, are output to a data error detection and correction part 60. The corrected data values are output to the processor and other parts of the system 70.
[0076] When a substantial amount of `errors` is being detected, e.g. in which way and how frequently the error correction schemes had to be applied, this can then be followed by re-writing the reference elements 220, after which data can be re-read. The amount of errors should be substantially reduced, if the problem had to do with the stability of the reference cells 130. This may also be implemented when memory elements 210 and reference elements 220 are identical.
Regarding Claim 35, control when the fatal external magnetic field is applied to the MTJ array and is removed from the MTJ array; [0069] FIG. 6 shows a graph of the H.sub.1 component as a function of the H.sub.2 component of the generated effective magnetic field for the reference elements 220. The curve on the graph shows a minimum amount of each of the effective magnetic field components to give a sufficient effective magnetic field for writing. The dotted line represents the line of points where the two components are equal.
Regarding Claims 36, 37, correct the memory data by overwriting the memory data with corrected memory data; and determine at what strength the magnetic field the data is uncorrectable. [0063] FIG. 3. Also shown is a detector 180 for detecting an abnormal level of data errors “data is uncorrectable” based on the read data values output by a data error detection and correction part 60. The data detection and/or correction may be carried out using a number of conventional techniques which are known by a skilled person and hence, do not need to be described here in more detail.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Hassner et al. (US 20230101414) [0107] Data is written to an MRAM memory cell by programming the free layer 807 to either have the same orientation or opposite orientation. An array of MRAM memory cells may be placed in an initial, or erased, state by setting all of the MRAM memory cells to be in the low resistance state in which all of their free layers have a magnetic field orientation that is the same as their reference layers. Each of the memory cells is then selectively programmed (also referred to as “written”) by placing its free layer 807 to be in the high resistance state by reversing the magnetic field to be opposite that of the reference layer 803.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: January 29, 2026
Final Rejection 20260128
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV