DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
1. The specification is objected because of the following reasons:
In par. [0001]: insert US Patent no. 12232307.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 1-3, 6, 7, 10-16 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2012/0098123).
Re claim 1, Yu teaches, under BRI, Figs. 1, 4 & 5, [0019-0023, 0027], a method of forming a chip package structure, comprising:
-providing a redistribution structure (interposer 21) including redistribution-side bonding structures (41) thereupon;
-providing a plurality of semiconductor dies (15, 17) including a respective set of die-side bonding structures (26);
-bonding the plurality of semiconductor dies (15, 17) to the redistribution structure (21) using first solder material portions (23) that are bonded to a respective redistribution-side bonding structure (41) within a first subset (left & right) of the redistribution-side bonding structures (41) and to a respective one of the die-side bonding structures (26), wherein a second subset (center) of the redistribution-side bonding structures (41) is not bonded to any of the plurality of semiconductor dies (15, 17); and
-forming a first underfill material portion (18) around the first solder material portions (23), the redistribution-side bonding structures (41), and the die-side bonding structures (26).
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Re claim 2, Yu teaches, Fig. 1, forming the first solder material portions (23) on the first subset (left & right) of the redistribution-side bonding structures (41); and forming additional first solder material portions (24) on the second subset (center) of the redistribution-side bonding structures (41), wherein the additional first solder material portions (24) are not bonded to any of the die-side bonding structures (26).
Re claim 3, Yu teaches, Fig. 1, wherein the first underfill material portion (18) laterally surround, and contacts, each of the additional first solder material portions (24).
Re claim 6, Yu teaches, under BRI, Figs. 1, 4 & 5, [0019-0023, 0027], a method of forming a chip package structure, comprising:
-providing a redistribution structure (21) comprising redistribution-side bonding structures (41); and
-attaching a plurality of semiconductor dies (15, 17) comprising a respective set of die-side bonding structures (26) by bonding the respective set of die-side bonding structures (26) to a respective subset of the redistribution-side bonding structures (41) through a respective set of first solder material portions (23), wherein a subset (at center) of the redistribution-side bonding structures is located between a neighboring pair of semiconductor dies (15, 17) selected from the plurality of semiconductor dies in a plan view and does not have any areal overlap with the plurality semiconductor dies (15, 17) in the plan view.
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Re claim 7, Yu teaches, Fig. 1, [0019], forming a first underfill material portion (18) around the redistribution-side bonding structures (41) and the die-side bonding structures (26) of the plurality of semiconductor dies (15, 17).
Re claim 10, Yu teaches, Fig. 1, wherein: the subset (at center) of the redistribution-side bonding structures (41) is not bonded to any of the die-side bonding structures (26) of the plurality of semiconductor dies (15, 17); and the method comprises forming a first underfill material portion (18) directly on a the subset of the redistribution-side bonding structures (41).
Re claim 11, Yu teaches, Fig. 1, wherein the first underfill material portion (18) is formed directly on sidewalls of the subset of the redistribution-side bonding structures (41).
Re claim 12, Yu teaches, Fig. 1, forming dummy solder material portions (24) on the subset (at center) of the redistribution-side bonding (41), wherein: the first underfill material portion (18) is formed directly on the dummy solder material portions (24); and all surfaces of the dummy solder material portions (24) are in contact with a respective surface selected from surfaces of the subset of the redistribution-side bonding structures (41) and surfaces of the first underfill material portion (18).
Note: in contact # directly/physically contact.
Re claim 13, Yu teaches, under BRI, Figs. 1, 4 & 5, [0019-0023, 0027], a method of forming a fan-out package, comprising:
-providing a redistribution structure (21) comprising a plurality of first metal bonding structures (41) on a first side;
-attaching a plurality of semiconductor dies (15, 17) comprising a plurality of second metal bonding structures (26) to the redistribution structure (21), wherein the plurality of second metal bonding structures (26) is attached to a first subset (left & right) of the plurality of first metal bonding structures (41) through solder material portions (23), wherein a gap region (between 15, 17) is present between a neighboring pair of semiconductor dies (15, 17) among the plurality of semiconductor dies, and wherein a second subset (at center) of the plurality of first metal bonding structures (41) comprising a dummy metal bonding structure (under 24) is located within the gap region and does not have any areal overlap with the plurality of semiconductor dies (15, 17) in a plan view; and
-forming an underfill material portion (18) around the solder material portions (23), wherein the underfill material portion (18) comprises a horizontally-extending portion that laterally surrounds the first metal bonding structures (41) and the second metal bonding structures (26) of the plurality of semiconductor dies (15, 17) and contacts each of the solder material portions (23), and further comprises a vertically-extending portion (e.g., vertically from layer 25 to layer 16) that fills the gap region (between 15, 17).
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Re claim 14, Yu teaches, Fig. 1, wherein the vertically-extending portion (of 18 extends from layer 25 to layer 16) is adjoined to the horizontally-extending portion, and contacts sidewalls of the neighboring pair of semiconductor dies (15, 17).
Note: contact # directly/physically contact.
Re claim 15, Yu teaches, Fig. 1, wherein the dummy metal bonding structure (under 24) is electrically isolated from the plurality of semiconductor dies (15, 17) and the second metal bonding structures (26) by the underfill material portion (18).
Re claim 16, Yu teaches, Fig. 1, forming a dummy solder material portion (24) on the dummy metal bonding structure (under 24), wherein all surfaces of the dummy solder material portion (24) are contacted by a respective surface selected from surfaces of the dummy metal bonding structure (under 24) and surfaces of the underfill material portion (18) upon formation of the underfill material portion (18).
Note: connect # directly/physically connect.
Re claim 18, Yu teaches, Fig. 1, [0019], forming a molding compound die frame (13) around the plurality of semiconductor dies (15, 17).
3. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. (US 2020/0312770).
Re claim 1, Lu teaches, under BRI, Fig. 1G, [0024, 0025, 0029, 0031, 0042], a method of forming a chip package structure, comprising:
-providing a redistribution structure (10) including redistribution-side bonding structures (under B1) thereupon;
-providing a plurality of semiconductor dies (TD11, TD12, TD13) including a respective set of die-side bonding structures (C11, C12, C13);
-bonding the plurality of semiconductor dies (TD11, TD12, TD13) to the redistribution structure (10) using first solder material portions (B1) that are bonded to a respective redistribution-side bonding structure (under B1) within a first subset (left & right) of the redistribution-side bonding structures (under B1) and to a respective one of the die-side bonding structures (C11, C12, C13 ), wherein a second subset (center) of the redistribution-side bonding structures (at center with DP1, DP2) is not bonded to any of the plurality of semiconductor dies (TD11, TD12, TD13); and
-forming a first underfill material portion (UF1, UF2) around the first solder material portions (B1), the redistribution-side bonding structures (under B1), and the die-side bonding structures (C11, C12, C13).
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4. Claim 6 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shim et al. (US 2009/0170241).
Re claim 6, Shim teaches, under BRI, Fig. 2f, [0027], a method of forming a chip package structure, comprising:
-providing a redistribution structure (under dies, indicated) comprising redistribution-side bonding structures (34); and
-attaching a plurality of semiconductor dies (36, 40) comprising a respective set of die-side bonding structures (38, 42) by bonding the respective set of die-side bonding structures (38) to a respective subset of the redistribution-side bonding structures (34) through a respective set of first solder material portions (38, 42), wherein a subset (at center) of the redistribution-side bonding structures (34) is located between a neighboring pair of semiconductor dies (36, 40) selected from the plurality of semiconductor dies in a plan view and does not have any areal overlap with the plurality semiconductor dies (36, 40) in the plan view.
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Takeuchi et al. (US 2005/0184377).
The teachings of Yu have been discussed above.
Re claim 4, Yu teaches, Fig. 1, [0019], forming a molding compound die frame (13) around the plurality of semiconductor dies (15, 17).
Yu does not explicitly teach forming the mold compound die frame after formation of the first underfill material portion.
Takeuchi teaches, Figs. 2D-E, [0047-0048], forming the mold compound die frame (21) after formation of the first underfill material portion (43).
As taught by Takeuchi, one of ordinary skill in the art would utilize & modify the above teaching to form the mold compound die frame after formation of the first underfill material portion as claimed, because it aids in enhancing protection in the formed package.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Takeuchi in combination with Yu due to above reason.
Re claim 9, in combination cited above, Yu teaches, Fig. 1, [0019], forming a molding compound die frame (13) around the plurality of semiconductor dies (15, 17), wherein the molding compound die frame comprises a molding compound material (13); and Takeuchi teaches, Figs. 2C-E, the molding compound material (21) that is formed directly on a peripheral portion of a planar surface of the redistribution structure (23, 26, 42).
6. Claims 5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Lin et al. (US 2018/0366439).
The teachings of Yu have been discussed above.
Re claim 5, Yu does not explicitly teach attaching the redistribution structure to a package substrate using an array of second solder material portions; and forming a second underfill material portion around the array of second solder material portions between the redistribution structure and the package substrate.
Lin teaches, Fig. 1F, [0015-0016, 0025, 0026], attaching the redistribution structure (102, 117) to a package substrate (300) using an array of second solder material portions (B3); and forming a second underfill material portion (between 102 & 300) around the array of second solder material portions (B3) between the redistribution structure (102, 117) and the package substrate (300).
As taught by Lin, one of ordinary skill in the art would utilize & modify the above teaching to obtain a package substrate and second underfill material as claimed, because package substrate is known as essential feature in an integrated package structure and to achieve a desired completed package structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lin in combination with Yu due to above reason.
Re claim 8, in combination cited above, Lin teaches, Fig. 1F, [0025, 0026], attaching a package substrate (300) to the redistribution structure (102, 117) via an array of second solder material portions (B3).
7. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Huang et al. (US 2020/0203300).
The teachings of Yu have been discussed above.
Re claim 17, Yu does not explicitly teach wherein the dummy solder material portion is formed entirely underneath a horizontal plane including a horizontal interface between the horizontally-extending portion of the underfill material portion and a bottom surface of the first semiconductor die.
Huang teaches, Fig. 1B, [0036, 0047], the dummy solder material portion (115d) is formed entirely underneath a horizontal plane including a horizontal interface between the horizontally-extending portion of the underfill material portion (140) and a bottom surface of the first semiconductor die (120).
As taught by Huang, one of ordinary skill in the art would utilize & modify the above teaching to obtain the dummy solder material portion is formed entirely underneath a horizontal plane including a horizontal interface between the horizontally-extending portion of the underfill material portion and a bottom surface of the first semiconductor die as claimed, because it aids in improving the yield of bumps and solder balls within the formed package.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Huang in combination with Yu due to above reason.
8. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Paek et al. (US 2016/0111391).
The teachings of Yu have been discussed above.
Re claim 20, Yu teaches, Fig. 1, wherein the underfill material portion (18) directly on each sidewall of the dummy metal bonding structure (under 24).
Yu does not explicitly teach the underfill material portion is formed directly on each sidewall of the plurality of semiconductor dies.
Paek teaches, Fig. 3G, [0034], the underfill material portion (consider 130) is formed directly on each sidewall of the plurality of semiconductor dies (120).
As taught by Paek, one of ordinary skill in the art would utilize & modify the above teaching to obtain the underfill material portion is formed directly on each sidewall of the plurality of semiconductor dies as claimed, because it aids in improved electrical isolation and stability of the dies in the formed package.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Paek in combination with Yu due to above reason.
Allowable Subject Matter
9. Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
10. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al. (US 2018/0331087, Fig. 1) discloses a stacked semiconductor package including a plurality of chips and dummy pads.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 10/4/26
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