DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species II, FIG. 4B (claims 1-18, 21, and 22) in the reply filed on 8/21/26 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 17 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 17 includes the limitation “a bottom surface of the source-side doped region is
located within a horizontal plane including a bottom surface of the channel region; an annular top surface of the source-side doped region is located within a horizontal plane including a top surface of the channel region; and an upper portion of the source-side doped region laterally surrounds a bottom portion of the source structure that protrudes below the horizontal plane including the top surface of the channel region.”; however, this limitation is described in the originally filed parent application 17/368,869.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 is identical to claim 6.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In view of the 112 rejection above, claim(s) 1 thru 3, 9, 11 thru 18 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al US 2020/0227519 A1 in view of Ryu et al. US 10,529,859 B2. Song discloses (see, for example, FIG. 4) a semiconductor structure 100B comprising: a planar insulating spacer layer 112 located over a substrate 110; a semiconducting material layer 114 comprising a semiconducting material 114, a thin film transistor (TFT) gate dielectric layer 132, and a gate electrode 134 located over the planar insulating spacer layer 112; a dielectric layer 140 located over the semiconducting material layer 114, the TFT gate dielectric layer 132, and the gate electrode 134; and a source structure 150 and a drain structure 150 comprising a metallic fill material and vertically extending through the dielectric layer 140 and contacting end portions of the semiconducting material layer 114, wherein the end portions of the semiconducting material layer 114 comprise a source-side doped region 120B and a drain-side doped region 120B that include dopant atoms therein. In paragraph [0037], Song discloses the source-side doped region 120B and a drain-side doped region 120B includes dopant atoms therein. Song does not clearly disclose the dielectric layer being a dielectric matrix layer. However, Ryu discloses (see, for example, FIG. 2, and column 5, lines 21-31) a semiconductor structure comprising a dielectric matrix layer 192 such as flowable oxide, undoped silica glass, etc. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the dielectric layer being a dielectric matrix layer in order to have a material that is easily etchable to form contacts therein, and since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 2, see, for example, claim 14 wherein Song discloses the lattice constant
of the source and drain regions having a second lattice constant lower than the first lattice constant of the channel layer.
Regarding claim 3, and the limitation “wherein a predominant fraction of the dopants atoms is located in substitutional sites.”, Song in view of Ryu does not use the specific language “substitutional sites”; however, it was well known in the art that dopants typically take the sites of the base silicon atoms in a silicon substrate, as they dope the host silicon material by substituting and taking the substitutional site left by the silicon atoms, and therefore, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a predominant fraction of the dopants atoms being located in substitutional sites in order to form source-side and drain-side doped regions with low electrical resistance and minimal leakage that adequately conduct a channel therebetween.
Regarding claim 9, see, for example, paragraph [0037] wherein Song discloses phosphorus-doped silicon, etc.
Regarding claim 11, see, for example, the rejection for claim 1 above. Further, regarding the limitation “wherein each of the source structure and the drain structure extend below a horizontal plane including a top surface of the semiconducting material layer and contacts a respective sidewall of the semiconducting material layer.”, see, for example, FIG. 2 wherein Ryu discloses a structure 170 extending below a horizontal plane including a top surface of the semiconducting material layer 150 and contacts a respective sidewall of the semiconductor material layer 150. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have each of the source structure and the drain structure extend below a horizontal plane including a top surface of the semiconducting material layer and contacts a respective sidewall of the semiconducting material layer in order to increase the surface contact area and minimize contact resistance, which improves overall drive current of the semiconductor structure.
Regarding claim 12, see, for example, FIG. 4 wherein Song discloses the center portion of the semiconducting material layer CH being located between the source-side doped region 120B and the drain-side doped region 120B. In paragraph [0039], Song discloses the source and drain regions may include a material that is different from that of the channel layer.
Regarding claim 13, see, for example, paragraph [0039] wherein Song discloses the source and drain regions 120 may include a material having a lattice constant, which is lower than that of the channel layer.
Regarding claim 14, see, for example, FIG. 4 wherein Song discloses a horizontal surface of the semiconducting material layer 114 has a periphery that coincides with a periphery of the TFT gate dielectric layer 132; and the source-side doped region 120B is laterally spaced from a sidewall of the semiconducting material layer 114by a portion of the semiconducting material layer 114 having a same material composition as the channel region CH.
Regarding claim 15, see, for example, FIG. 4 wherein Song discloses all portions of the semiconducting material layer 114 that do not have any areal overlap with the source structure 150 or the drain structure 150 has a first thickness; and portions of the source-side doped region 120B and the drain-side doped region 120B that underlie a horizontal bottom surface of the source structure 150 or a horizontal bottom surface of the drain structure 150 has a second thickness that is less than the first thickness.
Regarding claim 16, see, for example, the rejection of claim 1 above, and paragraph [0039] wherein Song discloses the source and drain regions 120 may include a material that is different from that of the channel layer.
Regarding claim 17, see, for example, FIG. 3, and paragraph [0052] wherein Song discloses a bottom surface of the source-side doped region is located within a horizontal plane including a bottom surface of the channel region; an annular top surface 150 of the source-side doped region is located within a horizontal plane including a top surface of the channel region CH; and, and the rejection for claim 11 above wherein Ryu discloses an upper portion of the source-side doped region laterally surrounds a bottom portion of the source structure that protrudes below the horizontal plane including the top surface of the channel region.
Regarding claim 18, see, for example, FIG. 4 wherein Song discloses top surfaces of the source structure 150 and the drain structure 150 are located within a horizontal plane including a top surface of the dielectric matrix layer 140.
Regarding claim 21, see, for example, FIG. 4 wherein Song discloses the semiconducting material layer 114 contacts a top surface of the planar insulating spacer layer 112; the TFT gate dielectric layer 132 contacts a top surface of the semiconducting material layer 114; and the gate electrode 134 contacts a top surface of the TFT gate dielectric layer 132.
Claim(s) 4 thru 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al US 2020/0227519 A1 in view of Ryu et al. US 10,529,859 B2 as applied to claims 1-3, 9, 11-18, and 21 above, and further in view of Liao US 6,534,402 B1. Song in view of Ryu does not disclose the dopant atoms comprise a metallic element. However, Liao discloses (see, for example, FIG. 2D-2F) a semiconductor structure comprising dopant atoms 214. In the abstract, Liao discloses cobalt ions, etc, which is a metallic element. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the dopant atoms comprise a metallic element in order to reduce the contact resistance of the source-side doped region and drain-side doped regions.
Regarding claim 5, see, for example, the abstract wherein Liao discloses cobalt ions, etc.
which is a transition metal.
Regarding claims 6, 7, and the limitation “the channel region comprises a first stoichiometric metal oxide material that is free of the metallic element; and the source-side doped region and the drain-side doped region comprise a second stoichiometric dielectric metal oxide material that includes atoms of the metallic element.”, see, for example, paragraph [0039] wherein Song discloses an oxide material, and in FIG. 2D wherein Liao discloses metal dopant atoms 214 being implanted in source and drain areas not covered by the gate, and metal dopant atoms 214 not being implanted in the channel region covered by the gate 206, and therefore has atoms of a metallic element in the source-side doped region and drain-side doped region but not in the channel region.
Regarding claim 8, see, for example, paragraph [0039] wherein Song discloses the source and drain regions 120 may include a material having a lattice constant, which is lower than that of the channel layer. Further, including the metal dopants into the source and drain regions 120 forms a material different than the channel region, which produces the second stoichiometric metal oxide material having a second lattice constant that is different from the first lattice constant.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al US 2020/0227519 A1 in view of Ryu et al. US 10,529,859 B2 as applied to claims 1-3, 9, 11-18, and 21 above, and further in view of Horii et al. US 2008/0272357 A1. Song in view of Ryu does not disclose metal interconnect structures contacting the source structure and the drain structure; and at least one memory cell located on the metal interconnect structures. However, Horii discloses (see, for example, Fig. 11) a semiconductor structure comprising metal interconnect structures 119 contacting the source structure and the drain structure; and at least one memory cell 124 located on the metal interconnect structures 119. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have metal interconnect structures contacting the source structure and the drain structure; and at least one memory cell located on the metal interconnect structures in order to utilize the semiconductor structure in more robust device such as a memory, etc.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al US 2020/0227519 A1 in view of Ryu et al. US 10,529,859 B2 as applied to claim 1-3, 9, 11-18, and 21 above, and further in view of Dewey et al US 2019/0363193 A1. Song discloses each of the source-side via cavity and the drain-side via cavity being laterally offset inward from the sidewalls of the semiconducting material layer; however, Song in view of Ryu does not clearly disclose each sidewall of the TFT gate dielectric layer being vertically coincident with a respective sidewall of the semiconducting material layer. However, Dewey discloses (see, for example, FIG. 1C) a gate wherein each sidewall of the gate dielectric layer 120 being vertically coincident with a respective sidewall of the semiconducting material layer 110. It would have been obvious to one of ordinary skill in the art to have each sidewall of the TFT gate dielectric layer being vertically coincident with a respective sidewall of the semiconducting material layer in order to insulate the gate electrode from unnecessarily contacting the semiconductor material layer.
Regarding the limitation “the source structure is located in a source-side via cavity that
vertically extends through the dielectric matrix layer and into an upper end portion of the semiconducting material layer; the drain structure is located in a drain-side via cavity that vertically extends through the dielectric matrix layer and into another upper end portion of the semiconducting material layer”, see, for example, the rejection for claim 11 above.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
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Eugene Lee
August 29, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815
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