Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed application, Application No. 16/514373 and 18/360854, fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application.
The current claim 15 was not a part of the original disclosure in 16/514373.
The examiner notes that paragraph [0073] in the current specification has been amended and is different from paragraph [0073] in 18/360854 and paragraph [0072] in 16/514373.
The current claim 15 has been amended to include “removing trap defects around at least one of the high-k dielectric layer, the gate spacer, the substrate, the LDD regions and the contact plugs”.
The applicant has not provided support for “removing”.
The original specification, 16/514373, paragraphs [0012], [0029], [0041], [0050], [0051], [0069], [0071], [0072] all disclose “trap-repairing” not “removing trap defects around”.
This application repeats a substantial portion of prior Application No. 16/514373 and 18/360854, having priority to 7/17/2019, and adds disclosure not presented in the prior application. Because this application names the inventor or at least one joint inventor named in the prior application, it may constitute a continuation-in-part of the prior application. Should applicant desire to claim the benefit of the filing date of the prior application, attention is directed to 35 U.S.C. 120, 37 CFR 1.78, and MPEP § 211 et seq. The presentation of a benefit claim may result in an additional fee under 37 CFR 1.17(w)(1) or (2) being required, if the earliest filing date for which benefit is claimed under 35 U.S.C. 120, 121, 365(c), or 386(c) and 1.78(d) in the application is more than six years before the actual filing date of the application.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 15-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The current application is a continuation of 18/360854 which is a divisional of 17/739240 which is a divisional of 16/514373.
The current claim 15 was not a part of the original disclosure in 16/514373.
The current claim 15 has been amended to include “removing trap defects around at least one of the high-k dielectric layer, the gate spacer, the substrate, the LDD regions and the contact plugs”.”
The applicant has not provided support for “removing trap defects around” in the original specification.
The examiner notes that paragraph [0073] in the current specification has been amended and is different from paragraph [0073] in 18/360854 and paragraph [0072] in 16/514373.
The original specification, 16/514373, paragraphs [0013], [0030], [0041], [0042], [0051], [0052], [0070], [0072] all disclose “trap-repairing” not “removing trap defects around”.
MPEP 2163 I B discloses “New or amended claims which introduce elements or limitations that are not supported by the as-filed disclosure violate the written description requirement. See, e.g., In re Lukach, 442 F.2d 967, 169 USPQ 795 (CCPA 1971) (subgenus range was not supported by generic disclosure and specific example within the subgenus range); In re Smith, 458 F.2d 1389, 1395, 173 USPQ 679, 683 (CCPA 1972) (an adequate description of a genus may not support claims to a subgenus or species within the genus)”. In this case the original specification fails to disclose “removing trap defects around”.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 12,119,389 in view of claim 1 of U.S. Patent No. 11,764,284. Although the claims at issue are not identical, they are not patentably distinct from each other because the current application claims the same subject matter.
Claim 1 of 11,764,284
Claim 1 of current application
providing a substrate comprising a surface; … depositing a first dielectric layer and a second dielectric layer over the substrate and the strips
depositing a first dielectric layer and a second dielectric layer over a substrate
performing a first treatment by introducing a trap-repairing element on the first and second dielectric layers
and performing a first treatment by introducing a trap-repairing element into at least one of the gate spacer, the second dielectric layer, the substrate, the LDD regions and the ILD layer.
forming a dummy gate electrode over the second dielectric layer;
forming a dummy gate electrode over the second dielectric layer
forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer;
forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer
forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate;
and forming an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions
forming an inter-layer dielectric (ILD) layer over the replacement gate
Claim 1 of U.S. Patent No. 11,764,284 fails to disclose removing the dummy gate electrode and forming a replacement gate.
Claim 1 of U.S. Patent No. 12,119,389 disclose removing the dummy gate electrode and forming a replacement gate.
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (removing dummy gate and forming a replacement gate), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (the replacement gate would be formed).
Regarding claim 2 of the current application, claim 2 of U.S. Patent No. 12,119,389 disclose the forming of the dummy gate electrode comprises: depositing a gate electrode layer over the substrate; and patterning the gate electrode layer into the dummy gate electrode.
Regarding claim 3 of the current application, claim 3 of U.S. Patent No. 12,119,389 disclose the first treatment comprises introducing a hydrogen gas into the semiconductor device.
Regarding claim 4 of the current application, claim 4 of U.S. Patent No. 12,119,389 disclose second treatment is performed at a temperature below about 400 °C.
Regarding claim 5 of the current application, claim 5 of 12,119,389 disclose the second treatment is performed at a pressure between about 10 atm and about 20 atm.
Regarding claim 6 of the current application, claim 6 of 12,119,389 disclose the second treatment is performed subsequent to the depositing of the ILD layer.
Regarding claim 7 of the current application, claim 7 of U.S. Patent No. 12,119,389 disclose depositing a contact plug in the ILD layer, wherein the second treatment is performed subsequent to the depositing of the contact plug.
Regarding claim 8 of the current application, claim 8 of U.S. Patent No. 12,119,389 disclose the first treatment introduces a first element to perform the repairing, wherein the first element includes an electronegativity greater than that of a second element introduced in the second treatment.
Regarding claim 10 of the current application, claim 10 of U.S. Patent No. 12,119,389 disclose the first treatment and the forming of the LDD regions are performed concurrently.
Claim 10 of U.S. Patent No. 12,119,389 disclose depositing a first dielectric layer and a second dielectric layer in sequence over the fins prior to the forming of the dummy gate electrode.
Regarding claim 11 of the current application, claim 11 of U.S. Patent No. 12,119,389 disclose the first dielectric layer is an oxide layer and the second dielectric layer is a high-k dielectric layer.
Regarding claim 12 of the current application, claim 12 of U.S. Patent No. 12,119,389 disclose the forming of the fins on the substrate comprises: performing an etching operation on the substrate to form strips; depositing isolation regions between the strips; and recessing the isolation regions, wherein portions protruding from the isolation regions constitute the fins at upper portions of the respective strips.
Regarding claim 13 of the current application, claim 13 of U.S. Patent No. 12,119,389 disclose depositing a third dielectric layer over the dummy gate electrode and the gate spacer prior to the forming of the LDD regions.
Regarding claim 14 of the current application, claim 14 of U.S. Patent No. 12,119,389 disclose depositing a fourth dielectric layer over the dummy gate electrode and the gate spacer in a conformal manner subsequent to the forming of the LDD regions.
Claims 15-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15 of U.S. Patent No. 12,119,389 in view of claims 15-19 of U.S. Patent No. 11,764,284. Although the claims at issue are not identical, they are not patentably distinct from each other because the current application claims the same subject matter.
Claim 15 of 12,119,389 discloses
Claim 1 of current application
providing a substrate comprising a surface;
depositing a high-k dielectric layer over a substrate
forming a dummy gate electrode over the high-k dielectric layer;
forming a gate spacer to surround the dummy gate electrode
forming a gate spacer to surround the dummy gate electrode;
forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer
forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer;
forming a replacement gate through removing the dummy gate electrode
forming a replacement gate and removing the dummy gate electrode;
and forming contact plugs to electrically couple to the replacement gate and the source/drain regions
forming contact plugs electrically coupled to the replacement gate;
introducing a hydrogen gas to perform a first annealing operation on the semiconductor device (this would result in removing trap defects around at least one of the high-k dielectric layer, the gate spacer, the substrate, the LDD regions and the contact plugs)
and removing trap defects around at least one of the high-k dielectric layer, the gate spacer, the substrate, the LDD regions and the contact plugs.
U.S. Patent No. 12,119,389 fails to disclose depositing a high-k dielectric layer over a substrate forming a dummy gate electrode over the high-k dielectric layer.
Claim 15 of U.S. Patent No. 11,764,284 disclose depositing a high-k dielectric layer over a substrate forming a dummy gate electrode over the high-k dielectric layer.
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (forming a high k dielectric and forming the dummy gate over the high k dielectric), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (the high-k dielectric and dummy gate would be formed).
Regarding claim 16 of the current application, claims 16 of U.S. Patent No. 12,119,389 disclose depositing a dielectric layer stack over the substrate prior to the forming of the dummy gate electrode.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sassiat et al. (US 2014/0264349) in view of in view of Su et al. (US 2012/0270411), Hsieh et al. (US 2018/0174904) and “Introduction to Microfabrication” by Sami Franssila(cited in parent application 17/739240).
Regarding claim 1, Sassiat et al. disclose
depositing a first dielectric layer (bottom half of 104) and a second dielectric layer (top half of 104) over a substrate (101);
forming a dummy gate electrode (105)[dummy gate, 0058] over the second dielectric layer; forming a gate spacer (107) surrounding the dummy gate electrode [0048];
forming lightly-doped source/drain (LDD) (extension region, 108E)[0049, 0073](fig. 1B) regions in the substrate on two sides of the gate spacer;
forming source/drain regions (108D, fig 1C)[0051] in the respective LDD regions; removing the dummy gate electrode to form a replacement gate [0058, dummy gate replaced at later stage (i.e. after source/drain region formation)];
and performing a first treatment by introducing (220) a trap-repairing element (fluorine), [0061] into at least one of the gate spacer the surface and the LDD regions before the forming of the source/drain regions (fig. 2a).
Sassiat fails to disclose forming an inter-layer dielectric (ILD) layer over the replacement gate.
Hsieh et al. disclose replacement gate replacing the dummy gate [0012] and forming an inter-layer dielectric (ILD) (64) layer over the replacement gate (figs. 7-25).
Therefore it would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teaching of Sassiat et al. and Hsieh et al. because the ILD would allow multiple level of metalliztion which would allow one to route signals over transistors and reduce the area needed for wiring ( p 357 “Introduction to Microfabrication” by Sami Franssila).
Regarding claim 2, Sassiat et al. disclose depositing a gate electrode layer (105) over the substrate (101); and patterning the gate electrode layer into the dummy gate electrode subsequent to the first treatment [0047].
Regarding claim 6, Sassiat et al. Su et al. and Hsieh et al. disclose the invention above. Sassiat et al. Su et al. and Hsieh et al. fail to explicitly disclose the first treatment is performed subsequent to the depositing of the ILD layer. However, the examiner submits the “the first treatment is performed subsequent to the depositing of the ILD layer” would be obvious over the combination of Sassiat et al. Su et al. and Hsieh et al., as noted above regarding claim 1, since the applicant has not provided any new or unexpected results from the specific sequence. See MPEP 2144.04 IV C In reBurhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946) (selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results).
Regarding claim 7, Sassiat et al. Su et al. and Hsieh et al. disclose the invention above. Sassiat et al. Su et al. and Hsieh et al. fail to explicitly disclose depositing a contact plug in the ILD layer, wherein the first treatment is performed subsequent to the depositing of the contact plug. However, the examiner submits the “depositing a contact plug in the ILD layer, wherein the first treatment is performed subsequent to the depositing of the contact plug” would be obvious over the combination of Sassiat et al. Su et al. and Hsieh et al., as noted above regarding claim 1, since the applicant has not provided any new or unexpected results from the specific sequence. See MPEP 2144.04 IV C In reBurhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946) (selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results).
Claims 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sassiat et al. (US 2014/0264349) in view of in view of Su et al. (US 2012/0270411), Hsieh et al. (US 2018/0174904) and “Introduction to Microfabrication” by Sami Franssila as applied to claim 2 above and further in view of Lee et al. (US 2017/0229587) and Kim et al. (US 2016/0343709)
Sassiat et al. Su et al. and Hsieh et al. disclose the invention supra.
Sassiat et al. Su et al. and Hsieh et al. fail to disclose the first treatment comprises introducing a hydrogen gas into the semiconductor device (claim 3) the first treatment is performed at a temperature below about 400 degrees C (claim 4), the first treatment is performed at a pressure between about 10 atm and about 20 atm (claim 5).
Lee et al. disclose a hydrogen as annealing at a temperature below about 200-300 degrees C [0073], at a pressure between of about 20 atm [0073]. Kim et al. discloses introducing a hydrogen gas to perform a first annealing operation on the semiconductor device.
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (annealing with a hydrogen gas), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (the hydrogen would diffuse into the semiconductor device and the hydrogen gas in the annealing process repairs defects in the semiconductor layers and surface defects of the semiconductor layer [Kim et al., 0112].).
Claim 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sassiat et al. (US 2014/0264349) in view of Wu (US Patent 9,356,120), Su et al. (US 2012/0270411), Hsieh et al. (US 2018/0174904) and “Introduction to Microfabrication” by Sami Franssila (cited in parent application 17/739240).
Regarding claim 15 Sassiat et al. disclose providing a substrate(101) comprising a surface;
depositing a dielectric layer (104) over the substrate;
forming a dummy gate electrode (105)[dummy gate, 0058] over the dielectric layer;
forming a gate spacer (107) to surround the dummy gate electrode;
forming lightly-doped source/drain (LDD) (extension region, 108E)[0049, 0073](fig. 1B) regions in the substrate on two sides of the gate spacer;
forming source/drain regions in the respective LDD regions;
forming a replacement gate and removing the dummy gate electrode[0058, dummy gate replaced at later stage (i.e. after source/drain region formation)].
Sassiat fails to disclose a high k dielectric.
Wu discloses a high k dielectric (205) formed and pattererned with the dummy gate (figs 3-4).
Therefore it would have been obvious to one of ordinary skill in the art at the time the invention was made to combine Sassiat and Wu, because the high-k dielectric allows increased gate capacitance without the associated leakage effects (see https://en.wikipedia.org/wiki/High-%CE%BA_dielectric).
Sassiat et al. fails to disclose performing a first treatment by introducing a trap-repairing element, into the first and second dielectric.
Su et al. disclose performing a first treatment (annealing) by introducing a trap-repairing element (removing trap defects around)(nitrogen).
The combination of Sassiat et al. Wu and Su would result in the removing trap defects around at least one of the high-k dielectric layer, the gate spacer, the substrate, because Su disclose the same process (annealing with nitrogen) with same structure (i.e. a substrate[ Sassiat] or high-k [Wu]). Therefore, one of ordinary skill would expect the same results. See MPEP 2112.01 I “[w]here the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”
Therefore it would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine Sassiat, and Su et al. because the trap repairing element will lower the trap density in the gate dielectric [Su et al., 0025] compared to the conventional methods of forming a gate dielectric.
Sassiat fails to disclose forming contact plugs to electrically couple to the replacement gate and the source/drain regions.
Hsieh et al. disclose forming contact plugs (60, 98) to electrically couple to the replacement gate and the source/drain regions (fig 25).
Therefore it would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teaching of Sassiat et al. and Hsieh et al. because the plugs and the ILD would allow multiple level of metalliztion which would allow one to route signals over transistors and reduce the area needed for wiring ( p 357 “Introduction to Microfabrication” by Sami Franssila).
Allowable Subject Matter
Claim 20 is allowable.
The following is a statement of reasons for the indication of allowable subject matter: depositing a first dielectric layer and a high-k dielectric layer over a semiconductor fin; passivating the high-k dielectric layer using a nitrogen-containing plasma; forming a patterned dummy gate over the semiconductor fin subsequent to the passivating of the high-k dielectric layer; forming a second dielectric layer over the patterned dummy gate; etching a portion of the second dielectric layer; forming lightly-doped source/drain (LDD) regions in the semiconductor fin on two sides of the patterned dummy gate; performing a first ion implantation on the LDD regions with an element having an electronegativity greater than electronegativities of silicon and oxygen; forming source/drain regions in the respective LDD regions; performing a second ion implantation on the source/drain regions; performing a first annealing operation on the source/drain regions at a first temperature; forming a replacement gate by etching the patterned dummy gate; and subsequent to the first annealing operation, performing a second annealing operation in a hydrogen ambient at a second temperature less than the first temperature (claim 20)
.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY K SMITH whose telephone number is (571)272-1884. The examiner can normally be reached Monday-Friday, 10am-6pm.
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/BRADLEY SMITH/Primary Examiner, Art Unit 2817
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