DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-14 in the reply filed on 7/06/26 is acknowledged. Applicant has cancelled non-elected claims and newly added claims 21-26.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 4/08/26. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-14 and 21-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chou et al. (US PGPub 2008/0096343, hereinafter referred to as “Chou”).
Chou discloses the semiconductor device as claimed. See figures 1A-2H and corresponding text, where Hsu teaches, in claim 1, a semiconductor structure, comprising:
a p-type metal-oxide semiconductor (PMOS) region (202) and an n-type metal-oxide semiconductor (NMOS) region (204) (figures 2A and 2B; [0033-0034]);
first source/drain (S/D) features (210c) disposed in the PMOS region and second S/D features (208c) disposed in the NMOS region (figure 2B; [0034])
a first channel region (210a) connecting the first S/D features and a second channel region (208a) connecting the second S/D features; (figure 2B; [0034])
a first high-k metal gate stack (HKMG) (210) disposed over the first channel region (210a) and a second HKMG (208) disposed over the second channel region (208a); (figures 2C and 2D; [0035-0037])
first gate spacers (210d) disposed on sidewalls of the first HKMG and second gate spacers (208d) disposed on sidewalls of the second HKMG; (figures 2C and 2C; [0035-0037])
a first etch-stop layer (ESL) (212) disposed on the first S/D features and the first gate spacers and a second ESL (212) disposed on the second S/D features and the second gate spacers; (figures 2C and 2D; [0035-0037])
an oxide layer (216) disposed on the first ESL but not the second ESL; (figure 2D; [0036-0037]), and
an interlayer dielectric (ILD) layer disposed on the oxide layer (216) and the second ESL. (figure 2F; [0039])
Chou teaches, in claim 2, wherein the ILD layer includes a greater concentration of silicon dioxide than the oxide layer.
Chou teaches, in claim 3, wherein the ILD layer includes a less concentration of silicon oxide (SiO) than the oxide layer ([0039]).
Chou teaches, in claim 4, further comprising a S/D contact disposed over one of the first S/D features, wherein the S/D contact extends through the ILD layer, the first ESL, and the oxide layer ([0042]).
Chou teaches, in claim 5, wherein the oxide layer includes silicon oxide (SiO) at a first concentration and silicon dioxide (SiO.sub.2) at a second concentration greater than the first concentration ([0036]).
Chou teaches, in claim 6, wherein the oxide layer includes unoxidized silicon at a concentration of less than about 0.1% by weight ([0036])
Chou teaches, in claim 7, a semiconductor structure, comprising:
a source/drain (S/D) feature (208c, 210c) disposed over a semiconductor substrate;
a channel region (208a, 210a) connected to the S/D feature;
a metal gate stack (208, 210) disposed over the channel region;
a gate spacer (208d, 210d) disposed along a sidewall of the metal gate stack;
an etch-stop layer (ESL) (212) disposed along a first portion of a sidewall of the gate spacer (208d, 210d) and over the S/D features (208a, 210a);
an oxide liner (216) disposed along a sidewall and a top surface of the ESL (212); and
an interlayer dielectric (ILD) layer disposed over the oxide liner (216), wherein the oxide liner includes silicon oxide (SiO) at a first concentration and silicon dioxide (SiO.sub.2) at a second concentration greater than the first concentration (figures 2E-2F; [0038-0039]).
Chou teaches, in claim 8, wherein the ESL is substantially free of silicon oxide or silicon dioxide (figures 2C-2F; [0033-0039]).
Chou teaches, in claim 9, wherein the top surface of the ESL is directly above the S/D feature (figures 2C-2F; [0033-0039]).
Chou teaches, in claim 10, wherein the oxide liner is disposed on a second portion of the sidewall of the gate spacer (figures 2C-2F; [0033-0039]).
Chou teaches, in claim 11, wherein the ILD layer is a first ILD layer; and
wherein the semiconductor structure further comprises:
a second ILD layer disposed over the metal gate stack, the gate spacer, and the first ILD layer, and a S/D contact connected to the S/D feature and extending through the first ILD layer, the second ILD layer, the oxide liner, and the ESL (figures 2C-2F; [0033-0039]).
Chou teaches, in claim 12, wherein the oxide liner includes unoxidized silicon at a concentration of less than about 0.1% by weight (figures 2C-2F; [0033-0039]).
Chou teaches, in claim 13, wherein the channel region is a first channel region, the metal gate stack is a first metal gate stack, the gate spacer is a first gate spacer, and the sidewall of the ESL is a first sidewall of the ESL;
wherein the semiconductor structure further comprises:
a second channel region adjacent to the S/D feature, a second metal gate stack disposed over the second channel region, and a second gate spacer disposed along a sidewall of the second metal gate stack;
wherein the ESL extends between the first gate spacer and the second gate spacer; and
wherein the oxide liner extends between the first sidewall of the ESL and a second sidewall of the ESL (figures 2C-2F; [0033-0039]).
Chou teaches, in claim 14, wherein the oxide liner is disposed on a sidewall of the second gate spacer (figures 2C-2F; [0033-0039]).
Chou teaches, in claim 21, a semiconductor structure, comprising: (figures 2C-2F; [0033-0039])
a source/drain feature (208c, 210c);
a channel member (208a, 210a) adjacent to and connected to the source/drain feature;
a metal gate (208, 210) disposed over the channel member; a gate spacer disposed along a sidewall of the metal gate;
an etch stop layer (ESL) (212) disposed along a sidewall of the gate spacer and a top surface of the source/drain feature;
an oxide layer (216) disposed along a sidewall and a top surface of the ESL;
an interlayer dielectric (ILD) layer over the oxide layer; and
a conductive feature extending through the ILD layer, the oxide layer, and the ESL, and connected to the source/drain feature.
Chou teaches, in claim 22, wherein the ILD layer comprises a dielectric material and a non-metallic dopant species (figures 2C-2F; [0033-0039]).
Chou teaches, in claim 23, wherein the ILD layer has a first concentration of silicon oxide (SiO), and the oxide layer has a second concentration of SiO higher than the first concentration (figures 2C-2F; [0033-0039]).
Chou teaches, in claim 24, wherein a topmost surface of the oxide layer is higher than a topmost surface of the ESL (figures 2C-2F; [0033-0039]).
Chou teaches, in claim 25, wherein the conductive feature intersects with the topmost surface of the oxide layer and is disposed along a sidewall of the oxide layer (figures 2C-2F; [0033-0039]).
Chou teaches, in claim 26, wherein the ESL has a first thickness, and the oxide layer has a second thickness less than the first thickness (figures 2C-2F; [0033-0039]).
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 July 25, 2026
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