DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A in the reply filed on July 15, 2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first distance from the ILD layer to a bottom surface of the data protection layer is the same as a second distance from the ILD layer to a top surface of the first data storage element (Examiner notes there are no markers or indicators to show the distances) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9-14 and 33-34 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 9, “a first distance from the ILD layer to a bottom surface of the data protection layer is the same as a second distance from the ILD layer to a top surface of the first data storage element” does not appear to be disclosed in the specification. [0024] and [0028] of the instant application disclose a “distance” in reference to a protection region between a memory region and logic region, ΔD. [0025]-[0026] of the instant application disclose recesses of the surface of the interlayer dielectric (ILD) layer, RE1-3. [0021] of the instant application discloses a height differential between memory cells, ΔH. However, there is no reference to the distance between the ILD layer and elements within a memory cell. For purposes of Examination, Examiner will choose arbitrary points on the ILD layer surface.
Claims 10-14 and 33-34 would also be rejected as they are dependent on claim 9.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-14 and 33-34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 9, an interlayer dielectric (ILD) layer having a top surface arcing from a second memory cell to a first memory cell is claimed starting in line 9. The limitations that follow with regards to two distances starting from the ILD layer being the same is unclear. The distance limitations do not provide a point of reference for a distance endpoint location on the ILD layer. This is needed since the top surface has an arc and different endpoints points on the top surface would have different distances, see annotated figure for an example using Fig 3D of the instant application. For purposes of Examination, Examiner will choose arbitrary points on the ILD layer surface.
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Claims 10-14 and 33-34 would also be rejected as they are dependent on claim 9.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-27, 29, and 31-32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Peng et. al. (US 20210226118 A1), hereinafter Peng.
Regarding claim 21, Peng teaches a semiconductor structure (Fig 8 semiconductor device 50, [0014]) comprising: a substrate (Fig 8 substrate 60, [0017]); a first memory cell (Fig 8 middle MRAM cell 58, [0014]) disposed over the substrate (Fig 8 substrate 60, [0017]), wherein the first memory cell (Fig 8 middle MRAM cell 58, [0014]) comprises a first top electrode (Fig 8 middle top electrode layer 124, [0039]) disposed on a first data storage element (Fig 8 middle MTJ stack 134, [0044]); and a second memory cell (Fig 8 right MRAM cell 58, [0014]) disposed over the substrate (Fig 8 substrate 60, [0017]) and adjacent to (Fig 8) the first memory cell (Fig 8 middle MRAM cell 58, [0014]), wherein the second memory cell (Fig 8 right MRAM cell 58, [0014]) comprises a second top electrode (Fig 8 right top electrode layer 124, [0039]) disposed on a protection layer (Fig 8 protective mask 122, [0037]), and the protection layer (Fig 8 protective mask 122, [0037]) is disposed on (Fig 8) a second data storage element (Fig 8 right MTJ stack 134, [0044]).
Regarding claim 22, Peng teaches a bottom surface (Fig 8 interface of mask 122 and right electrode layer 120) of the protection layer (Fig 8 protective mask 122, [0037]) and a bottom surface (Fig 8 interface of middle electrode layer 124 and middle electrode layer 120) of the first top electrode (Fig 8 middle top electrode layer 124, [0039]) are at a common elevation (See annotated figure) above the substrate (Fig 8 substrate 60, [0017]).
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Regarding claim 23, Peng teaches a bottom surface (Fig 8 interface of mask 122 and right top electrode layer 124) of the second top electrode (Fig 8 right top electrode layer 124, [0039]) is elevated above (Fig 8) a bottom surface (Fig 8 interface of middle electrode layer 124 and middle electrode layer 120) of the first top electrode (Fig 8 middle top electrode layer 124, [0039]).
Regarding claim 24, Peng teaches the protection layer (Fig 8 protective mask 122, [0037]) is disposed on a top surface (Fig 8) of the second data storage element (Fig 8 right MTJ stack 134, [0044]).
Regarding claim 25, Peng teaches a semiconductor structure (Fig 8 semiconductor device 50, [0014]) comprising: a substrate (Fig 8 substrate 60, [0017]); a first wire (Fig 8 middle conductive feature 104 in memory region 50M, [0023]) and a second wire (Fig 8 right conductive feature 104 in memory region 50M, [0023]) laterally offset from the first wire (Fig 8 middle conductive feature 104 in memory region 50M, [0023]) and disposed over the substrate (Fig 8 substrate 60, [0017]); a first data storage element (Fig 8 middle MTJ stack 134, [0044]) aligned over the first wire (Fig 8 middle conductive feature 104 in memory region 50M, [0023]); and a second data storage element (Fig 8 right MTJ stack 134, [0044]) aligned over the second wire (Fig 8 right conductive feature 104 in memory region 50M, [0023]), and a protection layer (Fig 8 protective mask 122, [0037] and electrode layer 120, [0035]) aligned over the second data storage element (Fig 8 right MTJ stack 134, [0044]), wherein a top surface of the first data storage element (Fig 8 middle MTJ stack 134, [0044]), a top surface of the second data storage element (Fig 8 right MTJ stack 134, [0044]), and a bottom surface of the protection layer (Fig 8 protective mask 122, [0037] and electrode layer 120, [0035]) are disposed at a common elevation (Fig 8) over the substrate (Fig 8 substrate 60, [0017]).
Regarding claim 26, Peng teaches a first top electrode (Fig 8 middle top electrode layer 124 and electrode layer 120, [0039]) disposed on a top surface of (Fig 8) the first data storage element (Fig 8 middle MTJ stack 134, [0044]); and a second top electrode (Fig 8 right top electrode layer 124, [0039]) disposed on a top surface of (Fig 8) the second data storage element (Fig 8 right MTJ stack 134, [0044]), wherein the protection layer (Fig 8 protective mask 122, [0037] and electrode layer 120, [0035]) is disposed on a top surface of (Fig 8) the second data storage element (Fig 8 right MTJ stack 134, [0044]).
Regarding claim 27, Peng teaches a first memory cell (Fig 8 middle MRAM cell 58, [0014]) comprises the first top electrode (Fig 8 middle top electrode layer 124 and electrode layer 120, [0039]) and the first data storage element (Fig 8 middle MTJ stack 134, [0044]), a second memory cell (Fig 8 right MRAM cell 58, [0014]) comprises the second top electrode (Fig 8 right top electrode layer 124, [0039]), the protection layer (Fig 8 protective mask 122, [0037] and electrode layer 120, [0035]), and the second data storage element (Fig 8 right MTJ stack 134, [0044]), and wherein a height of the first memory cell is less than a height of the second memory cell.
Regarding claim 29, Peng teaches a first top electrode (Fig 8 middle top electrode layer 124 and electrode layer 120, [0039]) disposed on (Fig 8) the first data storage element (Fig 8 middle MTJ stack 134, [0044]); and a second top electrode (Fig 8 right top electrode layer 124, [0039]) disposed on (Fig 8) the second data storage element (Fig 8 right MTJ stack 134, [0044]), wherein a bottom surface of the second top electrode (Fig 8 right top electrode layer 124, [0039]) is elevated above (Fig 8) a bottom surface of the first top electrode (Fig 8 middle top electrode layer 124 and electrode layer 120, [0039]) relative to the substrate (Fig 8 substrate 60, [0017]).
Regarding claim 31, Peng teaches an interlayer dielectric (ILD) layer (Fig 8 IMD layer 108, [0026]) disposed over the first wire (Fig 8 middle conductive feature 104 in memory region 50M, [0023]) and the second wire (Fig 8 right conductive feature 104 in memory region 50M, [0023]); a first bottom electrode (Fig 8 middle electrode 132, [0044]) extending from (Fig 8) the ILD layer (Fig 8 IMD layer 108, [0026]) to the first data storage element (Fig 8 middle MTJ stack 134, [0044]); and a second bottom electrode (Fig 8 right electrode 132, [0044]) extending from (Fig 8) the ILD layer (Fig 8 IMD layer 108, [0026]) to the second data storage element (Fig 8 right MTJ stack 134, [0044]).
Regarding claim 32, Peng teaches a first via (Fig 8 middle conductive via 110, [0027]) disposed within the ILD layer (Fig 8 IMD layer 108, [0026]) extending from the first wire (Fig 8 middle conductive feature 104 in memory region 50M, [0023]) to the first bottom electrode (Fig 8 middle electrode 132, [0044]); and a second via (Fig 8 right conductive via 110, [0027]) disposed within the ILD layer (Fig 8 IMD layer 108, [0026]) extending from the second wire (Fig 8 right conductive feature 104 in memory region 50M, [0023]) to the second bottom electrode (Fig 8 right electrode 132, [0044]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-14, 28, and 33-34 are rejected under 35 U.S.C. 103 as being unpatentable over Peng et. al. (US 20210226118 A1), hereinafter Peng.
Regarding claim 9, Peng teaches a semiconductor structure (Fig 8 semiconductor device 50, [0014]) comprising: a substrate (Fig 8 substrate 60, [0017]); a first wire (Fig 8 middle conductive feature 104 in memory region 50M, [0023]), a second wire (Fig 8 right conductive feature 104 in memory region 50M, [0023]), and a third wire (Fig 8 left conductive feature 104 in logic region 50L, [0023]) elevated above the substrate (Fig 8 substrate 60, [0017]) at a common elevation (Fig 8), wherein the second wire (Fig 8 right conductive feature 104 in memory region 50M, [0023]) is between the first (Fig 8 middle conductive feature 104 in memory region 50M, [0023]) and third wires (Fig 8 left conductive feature 104 in logic region 50L, [0023]); a memory array (Fig 8 memory region 50M, [0015]) laterally offset from (Fig 8) the third wire (Fig 8 left conductive feature 104 in logic region 50L, [0023]) and comprising a first memory cell (Fig 8 middle MRAM cell 58, [0014]) and a second memory cell (Fig 8 right MRAM cell 58, [0014]) respectively overlying the first (Fig 8 middle conductive feature 104 in memory region 50M, [0023]) and second wires (Fig 8 right conductive feature 104 in memory region 50M, [0023]), wherein the first memory cell (Fig 8 middle MRAM cell 58, [0014]) comprises a first data storage element (Fig 8 middle MTJ stack 134, [0044]), and the second memory cell (Fig 8 right MRAM cell 58, [0014]) comprises a data protection layer (Fig 8 protective mask 122, [0037] and electrode layer 120, [0035]); and an interlayer dielectric (ILD) layer (Fig 8 IMD layer 108, [0026]) having a top surface arcing (Fig 8) from the second memory cell (Fig 8 right MRAM cell 58, [0014]) to the first memory cell (Fig 8 middle MRAM cell 58, [0014]), wherein a first distance from the ILD layer (Fig 8 IMD layer 108, [0026]) to a bottom surface of the data protection layer (Fig 8 protective mask 122, [0037] and electrode layer 120, [0035]) is the same (Examiner notes that since there is no point on the ILD layer claimed to start the distance measurement, one having ordinary skill in the art before the effective filing date of the claimed invention would choose arbitrary points on the surface of the IMD layer of Peng to achieve the same distances as claimed) as a second distance from the ILD layer (Fig 8 IMD layer 108, [0026]) to a top surface of the first data storage element (Fig 8 middle MTJ stack 134, [0044]).
Regarding claim 10, Peng as modified in claim 9 teaches a height of the first memory cell (Fig 8 middle MRAM cell 58, [0014]) is less than (136A is thicker than 136B, [0047]) that of the second memory cell (Fig 8 right MRAM cell 58, [0014]).
Regarding claim 11, Peng as modified in claim 9 teaches the ILD layer (Fig 8 IMD layer 108, [0026]) extends continuously across (Fig 8) the third wires (Fig 8 left conductive feature 104 in logic region 50L, [0023]) from a first side (Fig 8 right side of left conductive feature 104 in logic region 50L) of the third wires (Fig 8 left conductive feature 104 in logic region 50L, [0023]) to a second side (Fig 8 left side of left conductive feature 104 in logic region 50L) of the third wires (Fig 8 left conductive feature 104 in logic region 50L, [0023]) opposite the first side (Fig 8 right side of left conductive feature 104 in logic region 50L).
Regarding claim 12, Peng as modified in claim 9 teaches the top surface of the ILD layer (Fig 8 IMD layer 108, [0026]) has a U-shaped profile (Fig 8) between the first (Fig 8 middle conductive feature 104 in memory region 50M, [0023]) and second wire (Fig 8 right conductive feature 104 in memory region 50M, [0023])s.
Regarding claim 13, Peng as modified in claim 9 teaches the second memory cell (Fig 8 right MRAM cell 58, [0014]) comprises a top electrode (Fig 8 right top electrode layer 124, [0039]) and a second data storage element (Fig 8 right MTJ stack 134, [0044]), wherein the data protection layer (Fig 8 protective mask 122, [0037] and electrode layer 120, [0035]) is disposed directly on (Fig 8) the second data storage element (Fig 8 right MTJ stack 134, [0044]), and the top electrode (Fig 8 right top electrode layer 124, [0039]) is over the data protection layer (Fig 8 protective mask 122, [0037] and electrode layer 120, [0035]).
Regarding claim 14, Peng as modified in claim 13 teaches the first memory cell (Fig 8 middle MRAM cell 58, [0014]) comprises a top electrode (Fig 8 middle top electrode layer 124 and electrode layer 120, [0039]) disposed directly on (Fig 8) the first data storage element (Fig 8 middle MTJ stack 134, [0044]).
Regarding claim 28, Peng teaches a top surface of the first memory cell (Fig 8 middle MRAM cell 58, [0014]) is recessed relative to a top surface of the second memory cell (Fig 8 right MRAM cell 58, [0014]) by about 200-300 angstroms (mask 122 may be 200Å-500Å, [0061]; the height difference is caused by the thickness of the mask 122, [0047]).
Regarding claim 33, Peng as modified in claim 11 teaches the ILD layer (Fig 8 IMD layer 108, [0026]) has a first vertical thickness directly over the third wires (Fig 8 left conductive feature 104 in logic region 50L, [0023]) and a second vertical thickness at a center between the first (Fig 8 middle MRAM cell 58, [0014]) and second memory cells (Fig 8 right MRAM cell 58, [0014]), and wherein the first vertical thickness is greater than (Fig 8 distance D1) the second vertical thickness.
Regarding claim 34, Peng as modified in claim 9 teaches the second memory cell (Fig 8 right MRAM cell 58, [0014]) is an outermost memory cell of the memory array (MRAM array of MRAM cells, [0022]) along a lateral direction (Fig 8 right) from the first memory cell (Fig 8 middle MRAM cell 58, [0014]) toward the third wires (Fig 8 left conductive feature 104 in logic region 50L, [0023]).
Allowable Subject Matter
Claim 30 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The closest art is Peng et. al. (US 20210226118 A1), hereinafter Peng.
Peng fails to teach the protection layer is a dielectric material.
Examiner notes that Peng does teach a protective mask 122 is a dielectric material (silicon oxide, [0046]). However, based on Examiner’s interpretation of the protection layer having protective mask 122 and layer 120, there are two materials, only one of which is a dielectric material.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dutta et. al. (US 20210126051 A1) teaches a sacrificial metal layer may be used to protect underlying materials.
Lin et. al. (US 20180366517 A1) teaches that a metallic capping layer may be used to protect underlying materials.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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