Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 29-35 are rejected under 35 U.S.C. 102(a1) as being anticipated by Oh et al. (US 9,825,081; hereinafter Oh).
Regarding claim 29, Oh, in fig. 2B, discloses an integrated circuit (IC) package comprising: a first IC chip 200, wherein the first IC chip 200 comprises: a first semiconductor substrate 210; a first interconnect structure 220 underlying the first semiconductor substrate 210 on a frontside of the first semiconductor substrate 210; and a pad structure 320 inset into a backside of the first semiconductor substrate 210 that is opposite the frontside of the first semiconductor substrate 210, wherein the pad structure 320 comprises a pad body (the lateral portion of 320) and a first pad protrusion (the vertical portion 321/323 of VH); and a second IC chip 100 underlying and bonded to the first IC chip 200, on the frontside of the first semiconductor substrate 210; wherein the first semiconductor substrate 210 has a sidewall facing and bordering the first pad protrusion 321/323, and wherein the first pad protrusion 321/323 protrudes from the pad body 320 to the second IC chip 100.
Regarding claim 30, Oh discloses wherein the second IC chip 100 comprises a second semiconductor substrate 110, and wherein the first pad protrusion 321/323 extends through an entire thickness of the second semiconductor substrate 110 (fig. 2B).
Regarding claim 31, Oh discloses further comprising: a trench isolation structure extending into the frontside of the first semiconductor substrate 250 and underlying the sidewall of the semiconductor substrate 210 (fig. 2B).
Regarding claim 32, Oh discloses wherein the pad structure 320 comprises a second pad protrusion 321/323, and wherein the second pad protrusion 321/323 protrudes from the pad body 320 to the second IC chip 100 (fig. 2B).
Regarding claim 33, Oh discloses wherein a height of the first pad protrusion 321/323 is greater than a height of the first IC chip 200 (fig. 2B).
Regarding claim 34, Oh discloses wherein the second IC chip 100 comprises: a second semiconductor substrate 110; and a second interconnect structure 120 overlying the second semiconductor substrate 110, on a frontside of the second semiconductor substrate 110, and comprising a plurality of wires grouped into a plurality of wire levels 120, wherein the plurality of wire levels 120 correspond to different elevations, and wherein a wire level farthest from the second semiconductor substrate 110 amongst the plurality of wire levels 120 includes a wire 122 that directly contacts the first pad protrusion 321/323 (fig. 2B).
Regarding claim 35, Oh discloses wherein the second IC chip 100 comprises: a second semiconductor substrate 110; and a second interconnect structure 120 overlying the second semiconductor substrate 110, on a frontside of the second semiconductor substrate 110, and comprising a wire 122 and a plurality of vias extending from the wire 122, and wherein the plurality of vias separate the wire 122 from the first pad protrusion 321/323 and extend from the wire 122 to the first pad protrusion 321/323 (fig. 2B).
2. Claims 36-40 are rejected under 35 U.S.C. 102(a1) as being anticipated by Huang et al. (US 9,704,827; hereinafter Huang).
Regarding claim 36, Huang, in fig. 2A, discloses an integrated circuit (IC) chip comprising: a semiconductor substrate 224; a wire (the layer connect to the bottom 206b) underlying the semiconductor substrate 224 on a frontside of the semiconductor substrate 224; a columnar structure 206b/208b overlying and extending towards the semiconductor substrate 224 from the wire, wherein the columnar structure 206b/208b is conductive; and a pad structure 226 inset into a backside of the semiconductor substrate 224 that is opposite the frontside of the semiconductor substrate 224, wherein the pad structure 226 comprises a pad body (the lateral portion of 226 on 230) and a first pad protrusion (the vertical portion of 226 form on 216), wherein the pad body 226 is separated from the wire by a semiconductor portion of the semiconductor substrate 224, and wherein the first pad protrusion 226b protrudes through the semiconductor portion of the semiconductor substrate 224 to the columnar structure 206b/208b.
Regarding claim 37, Huang discloses further comprising: a plurality of columnar structures 206b/208b, including the column structure, wherein the plurality of columnar structures 206b/208b extend from the wire 216 to the first pad protrusion 226b and separate the wire 216 from the first pad protrusion 226b (fig. 2A).
Regarding claim 38, Huang discloses wherein the plurality of columnar structures 206b/208b are in a plurality of rows and a plurality of columns (fig. 2A).
Regarding claim 39, Huang discloses wherein the first pad protrusion 226b and the semiconductor substrate 224 have individual frontside surfaces that are level with each other, and wherein the column structure 206b/208b is a conductive contact (fig. 2A).
Regarding claim 40, Huang discloses wherein the IC chip further comprises: an additional wire 216 that is closer to the semiconductor substrate 224 than the wire, wherein the columnar structure 206b/208b is a conductive via (fig. 2A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 21-28 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 9,704,827) in view of Tsai et al. (US 8,435,824; hereinafter Tsai).
Regarding claim 21, Huang, in fig. 7, discloses an integrated circuit (IC) chip, comprising: a semiconductor substrate 704; a wire 216/220 underlying the semiconductor substrate 704 on a frontside of the semiconductor substrate 704; an isolation structure 716 extending into the frontside of the semiconductor substrate 704; and a pad structure 226 inset into a backside of the semiconductor substrate 704 that is opposite the frontside of the semiconductor substrate 704, wherein the pad structure 226 comprises a pad body (the lateral portion of 222 on 706) and a first pad protrusion (the vertical portion of 226 form within and above 716), wherein the pad body 226 overlies and is spaced from the wire 216/220 by a semiconductor portion of the semiconductor substrate 704 (the semiconductor portion 704 between the 214 and 716) and the isolation structure 716, and wherein the first pad protrusion 226 protrudes through the semiconductor portion of the semiconductor substrate 704 and the isolation structure 716 to the wire 216/220 from the pad body 226.
Huang discloses a semiconductor device as above but fails to disclose the isolation structure is a trench isolation structure.
However, Tsai discloses the isolation structure 222 is a trench isolation structure 222 (fig. 8). In view of such teaching, it would have been obvious to the ordinary artisan at the time the invention was made to have modified the trench isolation structure as taught by Tsai because it would have been considered a well-known art recognized equivalent structure for the purpose of forming an isolation structure to isolate adjacent devices within the IC. Moreover, the substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Line Air Products Co. 85 USPQ 328 (USSC 1950).
Regarding claim 22, Huang discloses wherein the pad structure 226 further comprises a second protrusion 712 that is separated from the first pad protrusion 226 by the semiconductor portion of the semiconductor substrate 704, and wherein the second protrusion protrudes 712 through the semiconductor portion of the semiconductor substrate 704 and the trench isolation structure 716 to the wire 216/220 from the pad body 226 (fig. 7).
Regarding claim 23, Huang discloses wherein a width of the trench isolation structure 716 is less than a width of the pad body 712/226 (fig. 7).
Regarding claim 24, Huang discloses further comprising: a dielectric spacer 706/708 overlying the trench isolation structure 716 and extending along the first pad protrusion 226 from the trench isolation structure 716 to the pad body 226, wherein the dielectric spacer 706/708 has a sidewall that faces the first pad protrusion 226 and that overlies and is edge to edge with a sidewall of the trench isolation structure 716 (fig. 7).
Regarding claim 25, Huang discloses wherein the sidewall of the dielectric spacer 706/708 and the sidewall of the trench isolation structure 716 directly contact the first pad protrusion 226 (fig. 7).
Regarding claim 26, Huang discloses further comprising: a dielectric spacer 706/708 separating the first pad protrusion 226 from the trench isolation structure 716 and the semiconductor portion of the semiconductor substrate 704, wherein the dielectric spacer 706/708 extends from the pad body 226 to a frontside surface of the dielectric spacer 706/708, and wherein the frontside surface of the dielectric spacer 706/708 is level with a frontside surface of the trench isolation structure 716 (fig. 7).
Regarding claim 27, Huang discloses wherein a height of the first pad protrusion 226 is greater than a sum of a height of the trench isolation structure 716 and a height of the semiconductor portion of the semiconductor substrate 704 (fig. 7).
Regarding claim 28, Huang discloses further comprising: a plurality of wires 214/220 grouped into a plurality of wire levels, wherein the plurality of wire levels correspond to different elevations, and wherein a wire level 220 farthest from the semiconductor substrate 704 amongst the plurality of wire levels includes the wire (fig. 7).
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818
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