DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 11, 17 and 18 are objected to because of the following informalities:
The verb “comprises” in claim 11, line 1, claim 17, line 1 and claim 18, line 2 should be “comprise”.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 2 and 4-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 12,067,294. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 2 and 4-19 would have been obvious over claims 1-17 of the patent.
Regarding claim 2, claim 1 of the patent recites a data buffer device comprising:
a first serial interface (claim 1, line 2, at least one serial data terminal), it would have been obvious to one having ordinary skill in the art to recognize that the at least one serial data terminal is a terminal of a first serial data interface;
a first parallel interface, it would have been obvious to one having ordinary skill in the art to recognize that there is a first parallel interface to output the parallel dataand the DQS signal; and
an interface circuit coupled between the first serial interface and the first parallel interface, wherein the interface circuit is to:
receive a serial data stream from the first serial interface (claim 1, lines 3-5), the serial data stream comprising header fields inserted into the serial data stream (claim 1, lines, wherein the header fields specify data strobe (DQS) preamble information (claim 1, lines 7-10); convert the serial data stream to parallel data and a DQS signal associated with the parallel data using the header fields; and output the parallel data and the DQS signal on the first parallel interface (claim 1, lines 6-7).
Regarding claim 4, claim 2 of the patent recites the data buffer device of claim 2, wherein the interface circuit is a serializer- deserializer (SerDes) circuit (the deserializer receives serial data stream from a serializer.
Regarding claim 5, claim 2 of the patent recites the data buffer device of claim 2, wherein the interface circuit comprises: a deserializer circuit to receive the serial data stream and to convert the serial data stream into packets, wherein the packets comprise at least the parallel data and a preamble packet;
a latch coupled to an output of the deserializer circuit to store the packets;
a packet decoder coupled to the latch, the packet decoder to decode the packets and output the parallel data and the DQS signal;
a set of line drivers coupled to the packet decoder, the set of line drivers to drive data signals corresponding to the parallel data on a set of data lines of the first parallel interface; and
a strobe driver coupled to the packet decoder, the strobe driver to drive the DQS signal on a strobe line of the first parallel interface.
Regarding claim 6, claim 3 of the patent recites the data buffer device of claim 5, wherein the deserializer circuit comprises:
a first buffer to store a first portion of the packets according to a boundary indicator (claim 3, lines 6-7); and
a second buffer to store a second portion of the packets according to the boundary indicator, wherein the first portion and the second portion are barrel shifted out of the first buffer and the second buffer as an N-bit packet, where N is an integer greater than one (claim 3, lines 8-12).
Regarding claim 7, claim 4 of the patent recites the data buffer device of claim 5, wherein the deserializer circuit is a 1:N deserializer, where N is an integer greater than one.
Regarding claim 8, claim 5 of the patent recites the data buffer device of claim 5, wherein the packet decoder comprises a finite state machine (FSM).
Regarding claim 9, claim 6 of the patent recites the data buffer device of claim 2, wherein the interface circuit comprises:
a deserializer circuit to receive the serial data stream and to convert the serial data stream into packets, wherein the packets comprise at least the parallel data;
a set of latches coupled to an output of the deserializer circuit to store the packets over multiple clock cycles;
a multiplexer coupled to outputs of some of the set of latches;
a packet decoder coupled to an output of a first latch in the set of latches and an output of the multiplexer, the packet decoder to decode the packets and output the parallel data and the DQS signal;
a set of line drivers coupled to the packet decoder, the set of line drivers to drive data signals corresponding to the parallel data on a set of data lines of the first parallel interface; and
a strobe driver coupled to the packet decoder, the strobe driver to drive the DQS signal on a strobe line of the first parallel interface.
Regarding claim 10, claim 7 of the patent recites the data buffer device of claim 2, wherein the DQS preamble information is programmable to comprise at least one of a plurality of DQS patterns, each DQS pattern corresponding to a different clock cycle (tCKs) duration for a DQS period.
Regarding claim 11, claim 8 of the patent recites the data buffer device of claim 2, wherein the header fields comprises at least one synchronization (sync) packet, a preamble packet, and a start of data packet, wherein the sync packet comprises a first sequence of bits, the preamble packet comprises a second sequence of bits specifying the DQS preamble information, and the start of data packet comprises a third sequence of bits, wherein the first sequence, the second sequence, and the third sequence are different.
Regarding claim 12, claim 9 of the patent recites a memory system comprising:
a memory device that operates according to a parallel data and strobe scheme; and
an interface circuit to receive a serial data stream from a host device, the serial data stream comprising header fields that specify data strobe (DQS) preamble information, and convert the serial data stream to the parallel data and a DQS signal associated with the parallel data using the header fields, and output the parallel data and the DQS signal to the memory device.
Regarding claim 13, claim 10 of the patent recites the memory system of claim 12, wherein the interface circuit comprises:
a serial data terminal coupled to the host device; and
a set of parallel data terminals coupled to data terminals of the memory device; and
a strobe terminal coupled to a strobe terminal of the memory device.
Regarding claim 14, claim 11 of the patent recites the memory system of claim 13, wherein the interface circuit further comprises:
a deserializer circuit to receive the serial data stream and to convert the serial data stream into packets, wherein the packets comprise at least the parallel data and a preamble packet;
a latch coupled to an output of the deserializer circuit to store the packets;
a packet decoder coupled to the latch, the packet decoder to decode the packets and output the parallel data and the DQS signal;
a set of line drivers coupled to the packet decoder, the set of line drivers to drive data signals corresponding to the parallel data on the set of parallel data terminals; and
a strobe driver coupled to the packet decoder, the strobe driver to drive the DQS signal on the strobe terminal.
Regarding claim 15, claim 12 of the patent recites the memory system of claim 14, wherein the packet decoder comprises a finite state machine (FSM).
Regarding claim 16, claim 13 of the patent recites the memory system of claim 14, wherein the deserializer circuit is a 1:N deserializer, where N is an integer greater than one.
Regarding claim 17, claim 14 of the patent recites the memory system of claim 12, wherein the header fields comprises:
one or more synchronization packets, each synchronization packet comprising a first binary sequence of bits;
a synchronization and preamble packet comprising a second binary sequence of bits; and
a start of data transfer packet comprising a third binary sequence of bits.
Regarding claim 18, claims 15 and 16 of the patent recite the memory system of claim 12, wherein the header fields are one or more clock cycles in duration, wherein the header fields comprises zero or more synchronization packets, a synchronization and preamble packet, and a start of data transfer packet.
Regarding claim 19, claim 17 of the patent recites a method of operating an interface circuit of a data buffer device, the method comprising:
receiving, from a host device, a serial data stream over a first serial interface, the serial data stream comprising header fields inserted into the serial data stream, wherein the header fields specify data strobe (DQS) preamble information;
converting, using the header fields, the serial data stream to parallel data and a DOS signal associated with the parallel data; and
outputting, to a memory device, the parallel data and the DQS signal over a first parallel interface.
Allowable Subject Matter
Claims 3, 20 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “a second serial interface, wherein the first serial interface is a first host serial interface between a host device and the data buffer device, wherein the second serial interface is a second host serial interface between the host device and the data buffer device; and a second parallel interface, wherein the first parallel interface is a first memory device parallel interface between a memory device and the data buffer device, wherein the second parallel interface is a second memory device parallel interface between the memory device and the data buffer device.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 20, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “receiving, from the memory device, second parallel data over the first parallel interface; converting the second parallel data to a second serial data stream; and outputting, to the host device, the second serial data stream over the first serial interface.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 21, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “receiving, from the memory device, second parallel data over a second parallel interface; converting the second parallel data to a second serial data stream; and outputting, to the host device, the second serial data stream over a second serial interface.” in combination with the other limitations thereof as is recited in the claim.
Conclusion
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/HUAN HOANG/ Primary Examiner, Art Unit 2827