DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No 11,152,222. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following underlined limitations:
Pending claims
Claim 1, A semiconductor device, comprising:
a gate electrode separated from a substrate by a gate dielectric;
source/drain regions arranged within the substrate and on opposing sides of the gate electrode; and
a plurality of dielectric material structures arranged along an upper surface of the gate electrode, wherein the gate electrode extends along a bottom and one or more sides of respective ones of the plurality of dielectric material structures.
US 11,152,222 B2
1. A semiconductor device, comprising:
a semiconductor substrate;
a gate dielectric disposed over the semiconductor substrate;
a first source/drain region and a second source/drain region disposed in the semiconductor substrate and on opposite sides of the gate dielectric;
a gate electrode disposed over the gate dielectric; and
a plurality of dishing prevention structures embedded in the gate electrode, wherein: each of the plurality of dishing prevention structures is disposed within a perimeter of the gate electrode; each of the plurality of dishing prevention structures have a bottommost surface that is disposed vertically between an upper surface of the gate electrode and an upper surface of the gate dielectric; and each of the plurality of dishing prevention structures are laterally spaced from each other one of the plurality of dishing prevention structures.
3. The semiconductor device of claim 1, wherein: the plurality of dishing prevention structures comprise a dielectric material; and the gate electrode comprises a metal.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5 of U.S. Patent No 12,142,488 in view of KR 10-2004-0026240 A to KIM HYEONG HWAN, see attached including English translation, “Kim”. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following underlined limitations:
Pending claims
Claim 1, A semiconductor device, comprising:
a gate electrode separated from a substrate by a gate dielectric;
source/drain regions arranged within the substrate and on opposing sides of the gate electrode; and
a plurality of dielectric material structures arranged along an upper surface of the gate electrode, wherein the gate electrode extends along a bottom and one or more sides of respective ones of the plurality of dielectric material structures.
US 12,142,488
15. A semiconductor device, comprising:
a gate dielectric disposed on a substrate;
a gate electrode material separated from the substrate by the gate dielectric, wherein the gate electrode material comprises interior surfaces defining a first recess laterally surrounded by a second recess and a third recess, as viewed in a cross-sectional view;
a dishing prevention material disposed within the first recess, the second recess, and the third recess, the gate electrode material being vertically between the dishing prevention material and the gate dielectric; and
wherein the gate electrode material has a first thickness continuously and vertically extending from a bottom of the dishing prevention material within the third recess to a bottom of the gate electrode material and a second thickness continuously and laterally extending from a side of the dishing prevention material within the third recess to an outermost sidewall of the gate electrode material, the first thickness and the second thickness being non-zero thicknesses and the first thickness being larger than the second thickness.
5. The semiconductor device of claim 1, further comprising: source/drain regions disposed within the substrate on opposing sides of the gate electrode.
US 12,142,488 claims 5 and 1 fail to state wherein the dishing prevention material is a dielectric.
Kim teaches wherein a dishing prevention material (31) is a dielectric (English translation ¶ [0048]). It would have been obvious to one having ordinary skill in the art to have formed the device of US 12,142,488 claim 5 with the dishing prevention material as a dielectric as taught by Kim in order to select a material which prevents the dishing phenomenon (Kim English translation ¶ [0050]).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites “the top surfaces of the plurality of the one or more dielectric pillars” but the claimed “the plurality” lacks antecedent basis as claim 15 which recites “one or more dielectric pillars”. For purposes of examination, the language of claim 17 is interpreted as “wherein the one or more dielectric pillars comprises a plurality of dielectric pillars, the top surfaces of the plurality of the
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1,3,6 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by US 2014/0239417 A1 to Wang et al., “Wang”.
Regarding claim 1, Wang discloses a semiconductor device, comprising:
a gate electrode (226, ¶ [0010]) separated from a substrate (202, ¶ [0013]) by a gate dielectric (224, ¶ [0013]);
source/drain regions (204a, 204b, ¶ [0024]) arranged within the substrate and on opposing sides of the gate electrode; and
a plurality of dielectric material structures (four regions 216a in cross section, ¶ [0013],[0023]) arranged along an upper surface of the gate electrode (226), wherein the gate electrode (226) extends along (as viewed in cross section) a bottom and one or more sides of respective ones of the plurality of dielectric material structures (216a).
Regarding claim 3, Wang discloses the semiconductor device of claim 1, and Wang further discloses (FIG. 9A) wherein the gate electrode (226) has a first height (t1) and the plurality of dielectric material structures (216a) have a second height (t2), the second height (t2) being less than the first height t1).
Regarding claim 6, Wang discloses the semiconductor device of claim 1, and Wang further discloses (FIG. 9A) a dielectric (216b, ¶ [0023],[0024]) laterally surrounding the gate electrode (226), wherein the plurality of dielectric material structures (216a) have smaller heights (t2) than the dielectric (greater then t1).
Claim 15 is rejected under 35 U.S.C. § 102(a)(1) as being anticipated by US 2011/0073962 A1 to Chu et al., “Chu”.
Regarding claim 15, Chu discloses a semiconductor device (e.g. Fig. 6A,6B), comprising:
a metal gate electrode (67, ¶ [0019]) arranged over a substrate (35);
a gate dielectric (66, ¶ [0019]) arranged between the metal gate electrode (67) and the substrate (35);
source/drain regions (105 and 110, ¶ [0024]) arranged on opposing sides of the metal gate electrode (67); and
one or more dielectric pillars (98, ¶ [0023]) embedded within the metal gate electrode (67) and disposed along an upper surface of the metal gate electrode.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1,3-4,6,15-18 are rejected under 35 U.S.C. § 103 as being unpatentable over KR 10-2004-0026240 A to KIM HYEONG HWAN, see attached including English translation, “Kim”, in view of US 2015/0349125 A1 to CHEN, “Chen”.
Regarding claim 1, Kim discloses a semiconductor device (Drawing 2e, English translation page 5 “<Description of Symbols for Main Parts of Drawings>”), comprising:
a gate electrode (21) separated from a substrate (11) by a gate dielectric (19);
source/drain regions (15) arranged within the substrate (11) and on opposing sides of the gate electrode (21); and
a dielectric material structure (31) arranged along an upper surface of the gate electrode, wherein the gate electrode (21) extends along a bottom and one or more sides of the dielectric material structure (31).
Kim fails to clearly teach wherein the dielectric material (31) is a plurality of dielectric material structures.
Chen teaches wherein a dielectric material comprises a plurality of dielectric material structures (e.g. FIG. 1A,1B openings “A” in grid-shaped gate electrode 110 filled with ILD 150 in e.g. FIG. 3D, ¶ [0028],[0029],[0052],[0070]-[0071],[0086],[0103],[0110]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kim with the dielectric material formed of a plurality of dielectric material structures as taught by Chen in order to reduce the loading effect and therefore achieve uniform etch of the gate (Chen ¶ [0070],[0071],[0110]).
Regarding claim 3, Kim in view of Chen yields the semiconductor device of claim 1, and Kim further teaches wherein the gate electrode (21) has a first height and the dielectric material structure (31, plurality when applying teachings of Chen) have a second height, the second height being less than the first height (as pictured in Kim).
Regarding claim 4, although Kim in view of Chen yields the semiconductor device of claim 3, Kim as modified fails to clearly state wherein a ratio between the first height and the second height is between about 2:1 and about 5.
However, the drawings of Kim (Drawing 2e) show the first height (total height of the gate 21) to be at least twice the second height (height of 31).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kim in view of Chen with the relative heights as claimed as suggested by the drawings of Kim and/or since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the relative dimensions determine the shape and resulting electrical characteristics of the gate making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claim 6, Kim in view of Chen yields the semiconductor device of claim 1, and Kim further discloses a dielectric (sidewall spacers 13) laterally surrounding the gate electrode (21), wherein the dielectric material structure (plurality when applying teachings of Chen) have smaller height than the dielectric (31, since sidewall spacers 13 are shorter than 31).
Regarding claim 15, Kim discloses a semiconductor device (FIG. 2e, English translation page 5 “<Description of Symbols for Main Parts of Drawings>”), comprising:
a metal gate electrode (21) arranged over a substrate (11);
a gate dielectric (19) arranged between the metal gate electrode (21) and the substrate (11);
source/drain regions (15) arranged on opposing sides of the metal gate electrode (21); and
one or more dielectric elements (31) embedded within the metal gate electrode (21) and disposed along an upper surface of the metal gate electrode (21).
Kim fails to clearly teach wherein the dielectric element (31) is one or more dielectric pillars.
Chen teaches wherein a dielectric element comprises a plurality of dielectric pillars (e.g. FIG. 1A,1B openings “A” in grid-shaped gate electrode 110 filled with ILD 150 in e.g. FIG. 3D, ¶ [0028],[0029],[0052],[0070]-[0071],[0086],[0103],[0110]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kim with the dielectric element formed of a plurality of dielectric pillars as taught by Chen in order to reduce the loading effect and therefore achieve uniform etch of the gate (Chen ¶ [0070],[0071],[0110]).
Regarding claims 16 and 17, although Kim in view of Chen yields the semiconductor device of claim 15, Kim fails to clearly teach (claim 16) wherein a sum of surface areas of top surfaces of the one or more dielectric pillars is between about 5% and about 25% of a combined surface area of the upper surface of the metal gate electrode and the top surfaces of the one or more dielectric pillars, and (claim 17) wherein a surface area of the upper surface of the metal gate electrode is between about 75% and about 95% of the combined surface area of the upper surface of the metal gate electrode and the top surfaces of the plurality of the one or more dielectric pillars.
Chen teaches wherein a dielectric material comprises a plurality of dielectric material structures (e.g. FIG. 1A,1B openings “A” in grid-shaped gate electrode 110 filled with ILD 150 in e.g. FIG. 3D, ¶ [0028],[0029],[0052],[0070]-[0071],[0086],[0103],[0110]) and teaches wherein the loading effect may be affected by pattern density (¶ [0071]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kim in view of Chen with the ranges for the coverage of the dielectric pillars as suggested by the teachings of Chen since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the ranges determine the degree of loading effect making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claim 18, Kim in view of Chen yields the semiconductor device of claim 15, and Kim further discloses a first inter-level dielectric (ILD) layer (17) laterally surrounding the metal gate electrode, the one or more dielectric pillars (13) being a different dielectric material than the first ILD layer (inherently different since 17 has a different etch selectivity, Kim’s English translation [0045] “Referring to fig. 2e, the capping oxide layer 31, the tungsten layer 21,and the gate oxide layer 19 are polished by a cmp method using the interlayer insulating layer 17 as a polishing stop layer. In this case, a difference in etch selectivity with respect to the interlayer insulating layer 17 is 3 to 200 […]”).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0239417 A1 to Wang et al., “Wang”.
Regarding claim 4, although Wang anticipates the semiconductor device of claim 3, Wang fails to anticipate with sufficient specificity for anticipation (MPEP 2131.03) wherein a ratio between the first height (t1) and the second height (t2) is between about 2:1 and about 5.
However, Wang discloses wherein the ratio may be from 1.3:1 to 2:1 (1/0.75 to 1/0.5 ¶ [0035]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Wang with the ratio within the claimed range as taught by Wang since in case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), MPEP 2144.05, and/or since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the ratio determines the relative dimensions of the gate and therefore the resulting electrical properties making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Claim 5 is rejected under 35 U.S.C. § 103 as being unpatentable over US 2014/0239417 A1 to Wang et al., “Wang”, as applied to claim 1 above, and further in view of US 2013/0309857 A1 to Koburger, III et al., “Koburger”.
Regarding claim 5, Wang discloses the semiconductor device of claim 1, and although Wang discloses (FIG. 9A) wherein the gate electrode has a width (L1) arranged along a direction extending between the source/drain regions, Wang fails to clearly teach wherein the width (L1) is larger than 1.5 micrometers.
Koburger teaches (FIG. 7) wherein a gate width (w1) arranged along a direction extending between source/drain regions (15A,16A, ¶ [0036]) of several micrometers (microns) or more (¶ [0054]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Wang with the width within the claimed range as taught by Koburger in order to incorporate replacement work function materials into both narrow and wide gate cavities (Koburger ¶ [0002]-[0004]) and/or since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the gate width/length determines the resulting transistor size making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Claims 16-17 is rejected under 35 U.S.C. § 103 as being unpatentable over US 2011/0073962 A1 to Chu et al., “Chu”.
Regarding claim 16, although Chu anticipates the semiconductor device of claim 15, Chu fails to teach in sufficient specificity for anticipation (MPEP 2131.03) (claim 16) wherein a sum of surface areas of top surfaces of the one or more dielectric pillars is between about 5% and about 25% of a combined surface area of the upper surface of the metal gate electrode and the top surfaces of the one or more dielectric pillars, and (claim 17) wherein a surface area of the upper surface of the metal gate electrode is between about 75% and about 95% of the combined surface area of the upper surface of the metal gate electrode and the top surfaces of the plurality of the one or more dielectric pillars.
However, Chu shows in the drawings (e.g. Fig. 5B) wherein the dielectric pillars (98) occupy only a minor percentage of the overall gate (67) and teaches selecting dimensions of the openings for the dielectric pillars in order to prevent the openings from being “caved-in” (¶ [0023]) and prevent a sloped dielectric layer (98).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Chu with coverage percentages as claimed since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the dimensions of the dielectric pillars determines the resulting shape of the openings and shape of the dielectric pillars making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Claim 19 is rejected under 35 U.S.C. § 103 as being unpatentable over KR 10-2004-0026240 A to KIM HYEONG HWAN, see attached including English translation, “Kim”, in view of US 2015/0349125 A1 to CHEN, “Chen”, as applied to claim 18 above, further in view of US 2009/0020827 A1 to Mandelman et al., “Mandelman”.
Regarding claim 19, although Kim in view of Chen yields the semiconductor device of claim 18, Kim and Chen fail to clearly teach a second ILD layer disposed over the first ILD layer, top surfaces of the one or more dielectric pillars, and the upper surface of the metal gate electrode, wherein the second ILD layer laterally extends past outermost sidewalls of the metal gate electrode.
Mandelman teaches (e.g. FIG. 10B) a second ILD layer (200, ¶ [0024]) disposed over a first ILD layer (150, ¶ [0014]), top surface of a dielectric pillar (180, ¶ [0019]) and over a metal gate electrode (175, ¶ [0018]), wherein the second ILD layer (200) extends laterally past outermost sidewalls of the metal gate electrode (175).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kim in view of Chen with a second ILD as exemplified by Mandelman in order to provide an additional ILD for integrating source and drain contacts (Mandelman 195A, 195B ¶ [0024]) in order to provide electrical connections to the transistor.
Claim 20 is rejected under 35 U.S.C. § 103 as being unpatentable over KR 10-2004-0026240 A to KIM HYEONG HWAN, see attached including English translation, “Kim”, in view of US 2015/0349125 A1 to CHEN, “Chen”, as applied to claim 15 above, further in view of US 2010/0320529 A1 to Dong et al., “Dong”.
Regarding claim 20, although Kim in view of Chen yields the semiconductor device of claim 15, Kim and Chu fail to clearly teach wherein the metal gate electrode has a length extending between the source/drain regions and a width extending along a direction perpendicular to the length, the length being larger than the width.
Dong teaches (e.g. FIG. 3) wherein a gate electrode (106) has a length between source/drain regions (110 and 114, ¶ [0042],[0043]) and a width extending along a direction perpendicular to the length, the length being larger than the width (as pictured).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kim in view of Chen with the gate length longer than the width as taught by Dong in the process of applying the teachings of isolation edge implants (304) of Dong which suppressing a parasitic edge transistor and improving leakage currents (Dong Abstract, ¶ [0001]-[0014]) and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the relative gate dimensions determine the electrical characteristics of the gate (e.g. gate-channel overlap) making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Allowable Subject Matter
Claims 7-14 are allowed.
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art e.g. Wang anticipates claim 1 or generally teaches claim 1 as in Kim in view of Chen as discussed above. Prior art e.g. US 9,922,832 B1 to Han et al. teaches (FIG. 4) wherein upper surfaces of gates (300) and dielectrics (600) are curved after polishing (column 5 lines 1-27), prior art fails to reasonably teach or suggest wherein the gate electrode and the plurality of dielectric material structures respectively have curved upper surfaces facing away from the substrate as claimed in claim 2 together with all of the limitations of claim 1 as claimed.
Additionally, although prior art generally teaches dishing prevention structures as discussed above and prior art e.g. US 6,690,580 B1 to Goldberg et al. teaches (FIG. 5B,5C) varying the height of dielectric pillars (25h) in order to affect the resulting CMP profile, prior art fails to reasonably teach or suggest wherein the plurality of dishing prevention structures comprise a first dishing prevention structure and a second dishing prevention structure, bottoms of the first dishing prevention structure and the second dishing prevention structure being vertically separated from an upper surface of the gate dielectric by different distances, together with all of the limitations of claim 7 as claimed. Claims 8-14 are allowable insofar as they depend upon and include all of the limitations of allowable claim 7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2017/0294505 A1 to Shin et al. teaches (FIG. 3) wherein a gate electrode (150) includes a plurality of dielectric pillars (152, ¶ [0056],[0057]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/ Primary Examiner, Art Unit 2891
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