Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18779425 filed on 07/22/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
Applicant’s election without traverse of claims 1-20 in the reply filed on 6/5/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 10 recites the limitation “wherein the top surface of the conduction layer is located at a same level as a top surface of the upper semiconductor layer”. The metes and bounds of the claimed limitation can not be determined for the following reasons: Fig. 13 of the instant application clearly discloses that conduction layer 30a is NOT at a same level as a top surface of the upper semiconductor layer 213 (layer 33 is a well region).
Claim 11 recites the limitation “a shallow trench isolation (STI) structure disposed to surround the DTI structure and at an upper portion of the upper semiconductor layer opposite to the buried insulation layer”. The metes and bounds of the claimed limitation can not be determined for the following reasons: Fig. 13 of the instant application clearly discloses that the shallow trench isolation (STI) structure 214 is NOT at an upper portion of the upper semiconductor layer 213 (layer 33 is a well region) opposite to the buried insulation layer.
Allowable subject matter
Claim 20 is objected to as being dependent upon a rejected base claim (independent claim 14), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Dong (US 2019/0109039).
With respect to dependent claim 14, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein a top surface of the STI structure is located above a top surface of the semiconductor substrate, the top surface of the isolation layer is flush with the top surface of the STI structure, and the top surface of the conduction layer is located at a same level as the top surface of the semiconductor substrate”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Dong (US 2019/0109039) in view of Yang et al. (US 2015/0270333).
Regarding Independent claim 1, Dong teaches a semiconductor device, comprising:
a semiconductor substrate (Fig. 1, elements 101, 104, 106, paragraph 0010-0011);
a first isolation structure (Fig. 1, element 130, paragraph 0015) located at a first substrate portion of the semiconductor substrate; and
a second isolation structure (Fig. 1, element 160.sub.1-3, paragraph 0020) into a second substrate portion of the semiconductor substrate which is located beneath the first substrate portion (Fig. 1),
the second isolation structure including a conduction layer (Fig. 1, element 167, paragraph 0022) and an isolation layer (Fig. 1, element 165, paragraph 0021-0022) disposed to separate the conduction layer from the first substrate portion and the second substrate portion,
a top surface of the isolation layer being located at a higher level than a top surface of the conduction layer (Fig. 1, paragraph 0021-0022),
the isolation layer having an inclined lateral surface and an interconnecting region, which interconnects the inclined lateral surface and the top surface of the conduction layer (Fig. 1), and which has a width greater than 0 A and less than or equal to 100 A (Fig. 1 & 2f, paragraph 0043 discloses a width greater than 0 A and less than 1.5 um. “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05).
Dong does not explicitly disclose a second isolation structure formed to extend through the first isolation structure.
Yang et al. teach a semiconductor device comprising a second isolation structure (Fig. 1, element 36, paragraph 0022) formed to extend through the first isolation structure (Fig. 1, element 40, paragraph 0022).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Dong according to the teachings of Yang et al. with the motivation to improve breakdown voltage (paragraph 0012-0013).
Regarding claim 2, Dong modified by Yang et al. teach wherein an included angle between the inclined lateral surface of the isolation layer and the top surface of the conduction layer is greater than 90 degrees and smaller than 135 degrees (Fig. 1 f Dong odiscloses the angle greater than 90 degrees and less 180 degrees, “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05).
Regarding claim 3, Dong modified by Yang et al. teach wherein the included angle is in a range of 106 degrees to 118 degrees (Fig. 1 of Dong discloses the angle greater than 90 degrees and less 180 degrees, “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05).
Regarding claim 4, Dong modified by Yang et al. teach wherein the interconnecting region is coplanar with the top surface of the conduction layer (Fig. 1of Dong).
Regarding independent claim 14, Dong teaches a semiconductor device comprising:
a semiconductor substrate (Fig. 1, element 101, paragraph 0010);
a shallow trench isolation (STI) structure (Fig. 1, element 130, paragraph 0015) located at a first substrate portion of the semiconductor substrate; and
a deep trench isolation (DTI) structure (Fig. 1, element 160.sub.1-3, paragraph 0020) extending through a second substrate portion of the semiconductor substrate which is located beneath the first substrate portion,
the DTI structure including a conduction layer (Fig. 1, element 167, paragraph 0022) and an isolation layer (Fig. 1, element 165, paragraph 0021-0022) disposed to separate the conduction layer from the first and second substrate portions,
a top surface of the isolation layer being located at a higher level than a top surface of the conduction layer (Fig. 1, paragraph 0021-0022),
the isolation layer having an inclined lateral surface and an interconnecting region which interconnects the inclined lateral surface and the top surface of the conduction layer (Fig. 1), and
which is coplanar with the top surface of the conduction layer (Fig. 1).
Dong does not explicitly disclose a deep trench isolation (DTI) structure located in the STI structure.
Yang et al. teach a semiconductor device comprising a deep trench isolation (DTI) structure (Fig. 1, element 36, paragraph 0022) located in the STI structure (Fig. 1, element 40, paragraph 0022).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Dong according to the teachings of Yang et al. with the motivation to improve breakdown voltage (paragraph 0012-0013).
Regarding claim 15, Dong modified by Yang et al. teach wherein an included angle between the inclined lateral surface of the isolation layer and the top surface of the conduction layer is greater than 90 degrees and smaller than 135 degrees (Fig. 1 f Dong odiscloses the angle greater than 90 degrees and less 180 degrees, “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05).
Regarding claim 16, Dong modified by Yang et al. teach wherein the included angle is in a range of 106 degrees to 118 degrees (Fig. 1 of Dong discloses the angle greater than 90 degrees and less 180 degrees, “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05).
Regarding claim 17, Dong modified by Yang et al. teach wherein wherein the isolation layer includes a dielectric oxide material, and the conduction layer includes polysilicon (paragraph 0022 of Dong).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Dong (US 2019/0109039) in view of Yang et al. (US 2015/0270333) and further in view of Fuchs et al. (US 2022/0028727).
Regarding claim 5, Dong modified by Yang et al. teach all of the limitations as discussed above.
Dong modified by Yang et al. do not explicitly disclose wherein a seam is formed in the conduction layer.
Fuchs et al. teach a semiconductor device comprising a deep trench isolation (DTI) structure (Fig. 1, element 120, paragraph 0020) wherein a seam (Fig. 1, element 180, paragraph 0021) is formed in the conduction layer (Fig. 1, element 150, paragraph 0020).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Dong according to the teachings of Fuchs et al. with the motivation to prevent defect formation (paragraph 0003).
Claims 6-7, 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Dong (US 2019/0109039) in view of Yang et al. (US 2015/0270333) and further in view of Li et al. (US 10,460,982).
Regarding claims 6 & 18, Dong modified by Yang et al. teach all of the limitations as discussed above.
Dong modified by Yang et al. do not explicitly disclose wherein the semiconductor substrate includes: an upper semiconductor layer having the first substrate portion and the second substrate portion, a lower semiconductor layer disposed beneath the upper semiconductor layer, and a buried insulation layer disposed between the upper semiconductor layer and the lower semiconductor layer.
Li et al. teach a semiconductor device comprising an upper semiconductor layer (Fig. 10, element 106, Col. 5, lines 37-39) having the first substrate portion and the second substrate portion, a lower semiconductor layer (Fig. 10, element 102, Col. 5, lines 37-39) disposed beneath the upper semiconductor layer, and a buried insulation layer (Fig. 10, element 104, Col. 5, lines 37-39) disposed between the upper semiconductor layer and the lower semiconductor layer.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Dong and Yang et al. according to the teachings of Li et al. with the motivation to provide threshold voltage (Vt) tunability (Col. Lines 26-27).
Regarding claims 7 & 19, Dong modified by Yang et al. and Li et al. teach wherein the second isolation structure extends through the first isolation structure, the upper semiconductor layer and the buried insulation layer into the lower semiconductor layer (Fig. 10 of Li, DTI element 240-1 extends through elements 106, 104, and 102).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Dong (US 2019/0109039) in view of Yang et al. (US 2015/0270333) and in view of Li et al. (US 10,460,982) and further in view of Shank et al. (US 2020/0203478).
Regarding claim 8, Dong modified by Yang et al. and Li et al. teach all of the limitations as discussed above.
Dong modified by Yang et al. and Li et al. do not explicitly disclose wherein a doping region is formed in the lower semiconductor layer and is connected to the conduction layer.
Shank et al. teach a doping region (Fig. 1, element 120, 0048) is formed in the lower semiconductor layer (Fig. 1, element 122, 0018) and is connected to the conduction layer (paragraph 0048 discloses forming junction).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Dong and Yang et al. and Li et al. according to the teachings of Shank et al. with the motivation to provide a junction (paragraph 0048).
Claims 9, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Dong (US 2019/0109039) in view of Li et al. (US 10,460,982).
Regarding independent claim 9, Dong teaches a semiconductor device, comprising:
a semiconductor substrate including:
an upper semiconductor layer (Fig. 1, element 106, paragraph 0011),
a lower semiconductor layer (Fig. 1, element 101, paragraph 0010) disposed beneath the upper semiconductor layer, and
the DTI structure including a conduction layer (Fig. 1, element 167, paragraph 0022) and an isolation layer (Fig. 1, element 165, paragraph 0021-0022) disposed to separate the conduction layer from the upper semiconductor layer,
a top surface of the isolation layer being located at a higher level than a top surface of the conduction layer (Fig. 1, paragraph 0021-0022),
the isolation layer having an inclined lateral surface and an interconnecting region which interconnects the inclined lateral surface and the top surface of the conduction layer (Fig. 1), and
which is coplanar with the top surface of the conduction layer (Fig. 1).
Dong does not explicitly disclose a buried insulation layer disposed between the upper semiconductor layer and the lower semiconductor layer; a deep trench isolation (DTI) structure formed to extend through the upper semiconductor layer and the buried insulation layer into the lower semiconductor layer, the DTI structure including a conduction layer and an isolation layer disposed to separate the conduction layer from the buried insulation layer.
Li et al. teach a semiconductor device comprising a buried insulation layer (Fig. 10, element 104, Col. 5, lines 37-39) disposed between the upper semiconductor layer (Fig. 10, element 106, Col. 5, lines 37-39) and the lower semiconductor layer (Fig. 10, element 102, Col. 5, lines 37-39); a deep trench isolation (DTI) structure (Fig. 10, elements 240-1/240-2/240-3, Col. 7, lines 60-63) formed to extend through the upper semiconductor layer and the buried insulation layer into the lower semiconductor layer, the DTI structure including a conduction layer and an isolation layer disposed to separate the conduction layer from the buried insulation layer (the DTI structure of Dong would separate the conduction layer of Dong from the buried insulation layer of Li).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Dong according to the teachings of Li et al. with the motivation to provide threshold voltage (Vt) tunability (Col. Lines 26-27).
Regarding claim 13, Dong modified by Li et al. teach wherein the inclined lateral surface of the isolation layer interconnects the top surface and the interconnecting region of the isolation layer (Fig. 1 of Dong).
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Dong (US 2019/0109039) in view of Li et al. (US 10,460,982) and further in view of Yang et al. (US 2015/0270333).
Regarding claim 10, Dong modified by Li et al. teach all of the limitations as discussed above.
Dong modified by Li et al. do not explicitly disclose wherein the top surface of the conduction layer is located at a same level as a top surface of the upper semiconductor layer.
Yang et al. teach a semiconductor device comprising wherein the top surface of the conduction layer (Fig. 1, element 42, paragraph 0023) is located at a same level as a top surface of the upper semiconductor layer (Fig. 1, element 32, paragraph 0019).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Dong and Li et al. according to the teachings of Yang et al. with the motivation to improve breakdown voltage (paragraph 0012-0013).
Regarding claim 11, Dong modified by Li et al. and Yang et al. teach a shallow trench isolation (STI) structure (Fig. 1 of Yang, element 40, paragraph 0022) disposed to surround the DTI structure (Fig. 1 of Yang, element 36, paragraph 0022) and at an upper portion of the upper semiconductor layer (Fig. 1, element 32, paragraph 0019) opposite to the buried insulation layer (Fig. 1, element 30, paragraph 0019).
Regarding claim 12, Dong modified by Li et al. and Yang et al. teach wherein a top surface of the STI structure is at a same level as the top surface of the isolation layer (Fig. 1 of Yang).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813
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