DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10-11 and 13 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Tsai et al. (US 20150270342 from IDS), hereinafter Tsai.
Regarding claim 10, Tsai teaches a method (Abstract), comprising:
forming a fin-shaped structure (fig. 5A, structure with fin 104; para. 0019) extending from a substrate (substrate 102, semiconductor layer 103; para. 0022);
recessing a source/drain region (etching at operation 403) of the fin-shaped structure (104) to form a source/drain opening (opening over recess 127; para. 0074);
forming an undoped semiconductor layer (fig. 5C, silicon-containing epitaxial structure 285*; para. 0074) to fill a bottom portion of the source/drain opening (bottom portion of 127);
performing a pre-amorphization implantation (PAI) process (fig. 5E, PAI process 230*; para. 0069) to amorphize the undoped semiconductor layer (285*) and a part of the substrate (part of 103) disposed directly under the undoped semiconductor layer (285*), thereby forming an amorphous region (amorphized regions 232*; para. 0069);
forming a tensile stress film (fig. 5G, stress film 240*; para. 0070) over the amorphous region (232*);
performing an annealing process (annealing process 250*; para. 0071) to recrystallize the amorphous region (232*);
after the performing of the annealing process (250*), selectively removing the tensile stress film (fig. 5I, remove 240*); and
forming a source/drain feature (stressor regions 252*; para. 0071) over the recrystallized region (232*).
Regarding claim 11, Tsai further teaches the method of claim 10, wherein the source/drain feature (fig. 5I, 252*) comprises N-type dopants (dopants for n-type finFET devices; para. 0063).
Regarding claim 13, Tsai further teaches the method of claim 10, wherein the performing of the PAI process (fig. 5E, 230*) comprises implanting germanium (Ge), argon (Ar), xenon (Xe), carbon (C), or silicon (Si) (implant species Ar, Xe, As, P and Si).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 8-9 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Cheng et al. (US 20200266060 from IDS).
Regarding claim 1, Tsai teaches a method (Abstract), comprising:
forming a fin-shaped structure (fig. 5A, structure with fin 104; para. 0019) extending from a substrate (substrate 102, semiconductor layer 103; para. 0022);
recessing a source/drain region (etching at operation 403) of the fin-shaped structure (104) to form a source/drain opening (opening over recess 127; para. 0074);
performing a pre-amorphization implantation (PAI) process (fig. 5E, PAI process 230*; para. 0069) to amorphize a portion of the substrate (amorphized regions 232*; para. 0069) exposed by the source/drain opening (127);
forming a tensile stress film (fig. 5G, stress film 240*; para. 0070) over the substrate (103, 102);
performing an annealing process (annealing process 250*; para. 0071) to recrystallize the portion of the substrate (232*), the recrystallized portion of the substrate (232*) comprising dislocations (dislocations 260; para. 0052);
forming an epitaxial source/drain feature (stressor regions 252*; para. 0071) over the source/drain opening (127).
Tsai fails to explicitly teach the fin-shaped structure comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;
forming a gate structure wrapping around each of the plurality of channel layers.
However, Cheng teaches the fin-shaped structure (Cheng: fig. 1A, 3B, nanosheet stack structure 110; para. 0042, similar to 104 of Tsai) comprising a plurality of channel layers (Cheng: active nanosheet channel layers 112, 114, 116; para. 0040) interleaved by a plurality of sacrificial layers (Cheng: nanosheet layers 111, 113, 115, 117; para. 0044);
forming a gate structure (Cheng: fig. 1B, metal gate layer 174; para. 0077) wrapping around each of the plurality of channel layers (Cheng: 112, 114, 116).
Cheng and Tsai are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed method to add a plurality of channel layers interleaved by a plurality of sacrificial layers as taught by Cheng.
Doing so would realize a gate-all-around structure with more nanowire layers in a stacked configuration to increase the FET device width (or channel width), and thus the drive current (Cheng: para. 0002).
Regarding claim 2, Tsai in view of Cheng further teaches the method of claim 1, further comprising:
before the performing of the PAI process (Tsai: fig. 5C, 230*), forming an undoped epitaxial feature (Tsai: silicon-containing epitaxial structure 285*; para. 0074) over the source/drain opening (Tsai: 127),
wherein the PAI process (Tsai: 230*) further amorphizes the undoped epitaxial feature (Tsai: 285*).
Regarding claim 3, Tsai in view of Cheng further teaches the method of claim 1, wherein the performing of the PAI process (Tsai: fig. 5E, 230*) comprises implanting germanium (Ge), argon (Ar), xenon (Xe), carbon (C), or silicon (Si) (Tsai: implant species Ar, Xe, As, P and Si).
Regarding claim 4, Tsai in view of Cheng further teaches the method of claim 1, further comprising:
after the forming of the source/drain opening (Cheng: fig. 4B, opening of S/D region), performing an etching process (Cheng: fig. 5, recessing exposed sidewall; para. 0057) to selectively recess the plurality of sacrificial layers (Cheng: 111, 113, 115, 117) to form a plurality of inner spacer recesses (Cheng: recesses 110-R; para. 0057); and
forming a plurality of inner spacer features (Cheng: fig. 1A, embedded gate sidewall spacers 138; para. 0065) in the plurality of inner spacer recesses (Cheng: 110-R), respectively.
Regarding claim 8, Tsai in view of Cheng further teaches the method of claim 1, further comprising:
before the forming of the epitaxial source/drain feature (Tsai: fig. 5I, 252*), performing an etching process (Tsai: operation 410; para. 0076) to selectively remove the tensile stress film (Tsai: remove 240*).
Regarding claim 9, Tsai in view of Cheng further teaches the method of claim 1, wherein the tensile stress film (Tsai: fig. 5G, 240*) comprises silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), or silicon oxycarbonitride (SiOCN) (Tsai: silicon nitride, silicon oxide, silicon oxynitride; para. 0046).
Regarding claim 14, Tsai teaches the method of claim 10, wherein the recrystallized region (fig. 5I, 232*) comprises a dislocation (dislocations 260*; para. 0072) having a core (pinchoff points 262*; para. 0075) under the portion of the substrate (portion of 103).
Tsai fails to explicitly teach the fin-shaped structure comprises a stack of alternating channel layers interleaved by sacrificial layers and a portion of the substrate disposed directly under the stack.
However, Cheng teaches the fin-shaped structure (Cheng: fig. 1A, 3B, nanosheet stack structure 110; para. 0042, similar to 104 of Tsai) comprises a stack (110) of alternating channel layers (Cheng: active nanosheet channel layers 112, 114, 116; para. 0040) interleaved by sacrificial layers (Cheng: nanosheet layers 111, 113, 115, 117; para. 0044) and a portion of the substrate (Cheng: substrate 100; para. 0063) disposed directly under the stack (Cheng: 110).
Cheng and Tsai are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed method to add a stack of alternating channel layers interleaved by sacrificial layers as taught by Cheng.
Doing so would realize a gate-all-around structure with more nanowire layers in a stacked configuration to increase the FET device width (or channel width), and thus the drive current (Cheng: para. 0002).
Regarding claim 15, Tsai in view of Cheng further teaches the method of claim 14, further comprising:
after forming the source/drain opening (Cheng: fig. 4B, opening of S/D region), selectively recessing the sacrificial layers (Cheng: fig. 5, recessing 111, 113, 115, 117) to form inner spacer openings (Cheng: recesses 110-R; para. 0057); and
before forming the undoped semiconductor layer (Tsai: 240*), forming inner spacer features (Cheng: fig. 1A, embedded gate sidewall spacers 138; para. 0065) in the inner spacer openings (Cheng: 110-R).
Claims 12 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Li et al. (US 20070281413).
Regarding claim 12, Tsai teaches the method of claim 10 including the pre-amorphization implantation (PAI) process (fig. 5E, 230*).
Tsai fails to explicitly teach after the performing of the pre-amorphization implantation (PAI) process, performing another pre-amorphization implantation (PAI) process to enlarge the amorphous region.
However, Li teaches after the performing of the pre-amorphization implantation (PAI) process (Li: fig. 3, first pre-amorphization implantation (PAI); para. 0050, similar to 230* of Tsai), performing another pre-amorphization implantation (PAI) process (Li: second PAI; para. 0055) to enlarge the amorphous region (Li: amorphous regions 15 larger than amorphous regions 13; para. 0054, 0055).
Li and Tsai are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed method to add another pre-amorphization implantation (PAI) process as taught by Li
Doing so would realize second PAI with dual stressors further improving the electron mobility in the FETs (Li: para. 0069).
Regarding claim 17, Tsai teaches a method (Abstract), comprising:
forming a gate structure (fig. 5A, gate electrode layer 117; para. 0018) over a channel region (channel region 112; para. 0019) of a fin (fin 104; para. 0019);
forming a source/drain opening (opening over recess 127; para. 0074) extending into the fin (104), the source/drain opening (127) is adjacent to the channel region (112);
forming an undoped semiconductor layer (fig. 5C, silicon-containing epitaxial structure 285*; para. 0074) to fill a bottom portion of the source/drain opening (bottom portion of 127);
performing a first pre-amorphization implantation (PAI) process (fig. 5E, PAI process 230*; para. 0069) to amorphize the undoped semiconductor layer (285*), thereby forming an amorphous region (amorphized regions 232*; para. 0069);
forming a tensile stress film (fig. 5G, stress film 240*; para. 0070) over the enlarged amorphous region (enlarged 232*);
performing an annealing process (annealing process 250*; para. 0071) to recrystallize the enlarged amorphous region (enlarged 232*);
after the performing of the annealing process (250*), selectively removing the tensile stress film (fig. 5I, remove 240*); and
forming a source/drain feature (stressor regions 252*; para. 0071) over the recrystallized region (232*).
Tsai fails to explicitly teach performing a second pre-amorphization implantation (PAI) process to enlarge the amorphous region.
However, Li teaches performing a second pre-amorphization implantation (PAI) process (Li: fig. 3, second PAI; para. 0055) to enlarge the amorphous region (Li: amorphous regions 15 larger than amorphous regions 13; para. 0054, 0055).
Li and Tsai are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed method to add second pre-amorphization implantation (PAI) process as taught by Li
Doing so would realize second PAI with dual stressors further improving the electron mobility in the FETs (Li: para. 0069).
Regarding claim 18, Tsai in view of Li further teaches the method of claim 17, wherein the first PAI process and the second PAI process (Li: first and second PAI steps) implant different species (Li: different ions; para. 0057).
Regarding claim 19, Tsai in view of Li further teaches The method of claim 17, wherein implant energy of the second PAI process (Li: second PAI has about 1 KeV to about 25 KeV, choose 15KeV to 25KeV here; para. 0020) is greater than implant energy of the first PAI process (Li: first PAI has about 0.5 KeV to about 15 KeV; para. 0020).
Regarding claim 20, Tsai in view of Li further teaches the method of claim 17, wherein a portion of the enlarged amorphous region (Tsai: fig. 5I, part of 252*) is disposed directly under the channel region (Tsai: top part of 112).
Claims 5-7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Cheng as applied to claim 4 or 15 above, and further in view of Fang et al. (US 20150028355).
Regarding claim 5, Tsai in view of Cheng further teaches the method of claim 4, wherein the dislocations (Tsai: fig. 5I, 260) comprising a first dislocation (Tsai: 260*) having a dislocation core (Tsai: pinchoff points 262*; para. 0075).
Tsai in view of Cheng fails to explicitly teach the dislocation core is disposed directly under a bottommost inner spacer feature of the plurality of inner spacer features.
However, Fang teaches the dislocation core (Fang: fig. 9, pinchoff points 224 of dislocations 218; para. 0022, 0023, similar to 262* of Tsai) is disposed directly under a bottommost inner spacer feature (Fang: gate spacers 206; para. 0027, similar to 136, 138 of Cheng and Tsai: 262* below channel region 112) of the plurality of inner spacer features (Cheng: 136, 138).
Fang, Cheng and Tsai are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed method to add the dislocation core is disposed directly under a bottommost inner spacer feature as taught by Fang.
Doing so would realize a dislocation with increased stress to improve carrier mobility with improved uniformity of devices (Fang: para. 0030).
Regarding claim 6, Tsai in view of Cheng and Fang teaches the method of claim 5 including the dislocation core (Tsai: fig. 5I, 262*).
Tsai in view of Cheng and Fang according to claim 5 fails to explicitly a vertical distance between the bottommost inner spacer feature and the dislocation core is between about 10nm and about 30nm.
However, Tsai teaches a vertical distance (Tsai: fig. 5I, depths HD; para. 0053) between the bottommost inner spacer feature (Cheng: 138 below 136 as Tsai: spacers 111; para. 0029) and the dislocation core (Tsai: 262*) is less than about 10 nm to about 30 nm (Tsai: HD is about 10 nm to about 30 nm; para. 0053), which overlaps the distance range between about 10nm and about 30nm.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the distance range from less than about 10 nm to about 30 nm to between about 10nm and about 30nm.
Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Regarding claim 7, Tsai in view of Cheng and Fang teaches The method of claim 5 including the dislocation core (Tsai: fig. 5I, 262*).
Tsai in view of Cheng and Fang according to claim 5 fails to explicitly a horizontal distance between a bottommost portion of the gate structure and the dislocation core is between about 0.5nm and about 10nm.
However, Tsai in view of Cheng and Fang teaches a horizontal distance (Fang: fig. 9, horizontal distance of 224 to gate stacks 222; para. 0015) between a bottommost portion of the gate structure (Cheng: 174 below Fang: 222) and the dislocation core (Fang: 222) is less than 10nm (Cheng: recess depth R is about 10 nm; para. 0057 and Fang: 224 is below the spacer), which overlaps the distance range between about 0.5nm and about 10nm.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the distance range from less than 10nm to about 30 nm to between about 0.5nm and about 10nm.
Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Regarding claim 16, Tsai in view of Cheng teaches the method of claim 15 including the dislocation core (Tsai: fig. 5I, 262*).
Tsai in view of Cheng fails to explicitly teach the dislocation core is disposed directly under a bottommost inner spacer feature of the inner spacer features.
However, Fang teaches the dislocation core (Fang: fig. 9, pinchoff points 224 of dislocations 218; para. 0022, 0023, similar to 262* of Tsai) is disposed directly under a bottommost inner spacer feature (Fang: gate spacers 206; para. 0027, similar to 136, 138 of Cheng and Tsai: 262* below channgel region 112) of the inner spacer features (Cheng: 136, 138).
Fang, Cheng and Tsai are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed method to add the dislocation core is disposed directly under a bottommost inner spacer feature as taught by Fang.
Doing so would realize a dislocation with increased stress to improve carrier mobility with improved uniformity of devices (Fang: para. 0030).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
Prosecution Insights