DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 19 is objected to because of the following informalities:
The limitation “wherein the source via is formed to have a line-shaped top profile” of claim 19 should read “wherein the source via is formed to have arectangular-shaped top profile”. Which is supported by the specification.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 20200105761 A1; hereinafter Liaw) in view of Liaw (US 20190067131 A1; hereinafter Liaw2).
Regarding claim 16, FIGS. 5A-5D of Liaw a method comprising: forming a semiconductor layer (515S ¶ [0040]) extending lengthwise along a first direction (x direction) between an epitaxial source (545S) and an epitaxial drain (545S ¶ [0051]); forming a gate structure (585, 520, 580) extending lengthwise along a second direction (y direction ¶ [0044]), wherein the second direction (y direction) is different than the first direction (x direction), and further wherein: the gate structure (585, 520, 580) is disposed between the epitaxial source (545S) and the epitaxial drain (545S) along the first direction (x direction), the gate structure (585, 520, 580) includes a gate stack (585 ¶ [0044]), a first gate spacer (520 ¶ [0049]), a second gate spacer (520), and a gate hard mask (580 ¶ [0044]), the gate stack (585) is disposed between the first gate spacer (520) and the second gate spacer (520) along the first direction (x direction), the gate hard mask (580) is disposed over the gate stack (585), the first gate spacer (520), and the second gate spacer (520), and the gate stack (585) surrounds the semiconductor layer (515S); forming a source contact (550 ¶ [0055]) on the epitaxial source (545S) and abutting the first gate spacer (520) and the gate hard mask (580), wherein the first gate spacer (520) is disposed between the source contact (550) and the gate stack (585) and the source contact (550) extends lengthwise along the second direction (y direction); forming a drain contact (550 ¶ [0055]) directly on the epitaxial drain (545S) and abutting the second gate spacer (520) and the gate hard mask (580), wherein the second gate spacer (520) is disposed between the drain contact (550) and the gate stack (585) and the drain contact (550) extend lengthwise along the second direction (y direction); forming a gate via (560 ¶ [0055]) directly on the gate stack (585), wherein the gate via (560) extends through the gate hard mask (580), the gate hard mask (580) is disposed between the source contact (550) and the gate via (560), and the gate hard mask (580) is disposed between the drain contact (550) and the gate via (560); forming a source via (570 ¶ [0055]) directly on the source contact (550); forming a drain via (570 ¶ [0055]) directly on the drain contact (550); and the gate via (560) is disposed between the source via (570) and the drain via (570) along a lengthwise direction of the semiconductor layer (x direction, see FIG. 5A).
Liaw does not teach wherein the source via has a long-side source via dimension and a short-side source via dimension; wherein the drain via has a long-side drain via dimension and a short-side drain via dimension, wherein a ratio of the long-side source via dimension to the short-side source via dimension is greater than a ratio of the long-side drain via dimension to the short-side drain via dimension; and wherein the gate via is disposed directly above and overlaps the semiconductor layer, the gate via does not overlap edges of the semiconductor layer.
FIGS. 1A-D of Liaw2 teach a method comprising: forming a semiconductor layer (16 ¶ [0026]) extending lengthwise along a first direction (y direction) between an epitaxial source (40D) and an epitaxial drain (40B ¶ [0035]); forming a gate structure (30A) extending lengthwise along a second direction (x direction ¶ [0031]), wherein the second direction (x direction) is different than the first direction (y direction), and further wherein: the gate structure (30A) is disposed between the epitaxial source (40D) and the epitaxial drain (40B) along the first direction (y direction), the gate structure (30A) includes a gate stack (30A); forming a source contact (60D ¶ [0040]) directly on the epitaxial source (40D), wherein the source contact (60D) extends lengthwise along the second direction (x direction); forming a drain contact (60B ¶ [0040]) directly on the epitaxial drain (40B), wherein the drain contact (60B) extends lengthwise along the second direction (x direction); forming a gate via (70E ¶ [0042]) directly on the gate stack (30A, see FIG. 1D); forming a source via (70D ¶ [0041]) directly on the source contact (60D), wherein the source via (70D) has a long-side source via dimension (X1) and a short-side source via dimension (Y1 ¶ [0043]); forming a drain via (70B ¶ [0041]) directly on the drain contact (60B), wherein the drain via (70B) has a long-side drain via dimension (X2) and a short-side drain via dimension (Y2 ¶ [0043]), wherein a ratio of the long-side source via dimension (X1) to the short-side source via dimension (Y1, e.g. X1/Y1 > 2) is greater than a ratio of the long-side drain via dimension (X2) to the short-side drain via dimension (Y2, e.g. 1.2 > X2/Y2 > 0.8 ¶ [0043]); and wherein the gate via (70E) is disposed directly above and overlaps the semiconductor layer (16), the gate via (70E) does not overlap edges of the semiconductor layer (e.g. edges of 16 to the right of 70E as shown in FIG. 1D), and the gate via (70E) is disposed between the source via (70D) and the drain via (70B) along a lengthwise direction of the semiconductor layer (16 – y direction, see FIG. 1A).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught by Liaw with the interconnect structure taught by Liaw2 for the purpose of maintaining high performance while achieving high density (¶ [0023]).
Regarding claim 17, Liaw as modified teaches the method of claim 16, and FIG. 1A of Liaw2 further teaches wherein: the ratio of the long-side source via dimension (X1) to the short-side source via dimension (Y1) is about 1.2:1 to about 10:1 (e.g. X1/Y1 > 2 ¶ [0043]); and the ratio of the long-side drain via dimension (X2) to the short-side drain via dimension (Y2) is about 1:1 to about 1.2:1 (e.g. 1.2 > X2/Y2 > 0.8 ¶ [0043]).
Regarding claim 18, Liaw as modified teaches the method of claim 16, and FIG. 1A of Liaw2 further teaches wherein the gate via (70E) has a long-side gate via dimension (X3) and a short-side gate via dimension (Y3); and a ratio of the long-side gate via dimension (X3) to the short-side gate via dimension (Y3, e.g. X3/Y3 = 1.1) is less than the ratio of the long-side drain via dimension (X2) to the short-side drain via dimension (Y2, e.g. X2/Y2 = 1.2 ¶ [0043]).
Regarding claim 19, Liaw as modified teaches the method of claim 16, and Liaw2 further teaches wherein the source via (70D) is formed to have a line-shaped top profile (rectangular-shaped) and the drain via (70B) is formed to have a circular-shaped top profile (circular-shaped ¶ [0043]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Liaw2, and further in view of Bae et al. (US 20220336664 A1; hereinafter Bae).
Regarding claim 20, Liaw as modified teaches the method of claim 16.
Liaw does not teach wherein the source via, the drain via, and the gate via are formed of ruthenium.
FIGS. 1-4 of Bae teach a FinFET device including a source via (206), a drain via (206), and a gate via (207); and wherein the source via (206), the drain via (206), and the gate via (207) are formed of ruthenium (¶ [0116]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught by Liaw with the ruthenium vias taught by Bae for the purpose of reducing overall resistance compared to typical copper vias, opening the door to more flexible integration schemes, and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Allowable Subject Matter
Claims 1-15 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 1 recites a method comprising: receiving a semiconductor workpiece including: a stack of channel layers over a substrate, wherein the stack of channel layers extends lengthwise along a first direction, a source feature and a drain feature over the substrate, wherein the stack of channel layers extend between the source feature and the drain feature, and a gate structure over the substrate, wherein the gate structure extends along a second direction perpendicular to the first direction, the gate structure is disposed between the source feature and the drain feature, and the gate structure has a gate stack that engages the stack of channel layers; forming a gate via connected to the gate stack, wherein the gate via has a first dimension along the second direction and a second dimension along the first direction; forming a source via connected to the source feature, wherein the source via has a third dimension along the second direction and a fourth dimension along the first direction; forming a drain via connected to the drain feature, wherein the drain via has a fifth dimension along the second direction and a sixth dimension along the first direction; and wherein: a ratio of the third dimension to the fourth dimension is greater than a ratio of the fifth dimension to the sixth dimension, the first dimension is less than the fifth dimension and the second dimension is less than the sixth dimension, the ratio of the third dimension to the fourth dimension is greater than a ratio of the first dimension to the second dimension, and the gate stack has a gate stack width along the first direction, wherein the gate stack width is greater than the second dimension.
Liaw (US 20200105761 A1; hereinafter Liaw) teaches wherein the gate via has a first dimension along the second direction and a second dimension along the first direction.
Liaw (US 20120001232 A1; hereinafter Liaw1) teaches the first dimension is less than the fifth dimension and the second dimension is less than the sixth dimension.
Liaw (US 20190067131 A1; hereinafter Liaw2) teaches wherein the ratio of the fourth dimension to the third dimension is greater than a ratio of the second dimension to the first dimension. However, upon inverting the fraction to reflect the claim language Liaw2 does not teach the ratio of the third dimension to the fourth dimension is greater than a ratio of the first dimension to the second dimension.
Liaw (US 8952547 B2; hereinafter Liaw3) teaches a gate via which has smaller dimensions than the gate.
However, the prior art fails to teach or reasonably suggest “the ratio of the third dimension to the fourth dimension is greater than a ratio of the first dimension to the second dimension” together with all the limitations of claim 1 as claimed. Claims 2-10 are allowable insofar as they depend upon and require all the limitations of claim 1.
Claim 11 recites a method comprising: forming first semiconductor layers and second semiconductor layers; forming a first gate structure and a second gate structure extending along a gate direction, wherein each of the first gate structure and the second gate structure has a respective gate stack and respective gate spacers, wherein the respective gate spacers are disposed along sidewalls of the respective gate stack, the first gate structure wraps the first semiconductor layers, and the second gate structure wraps the second semiconductor layers; forming a first source feature and a second source feature; forming a common drain feature, wherein the first semiconductor layers are between the first source feature and the common drain feature, the second semiconductor layers are between the common drain feature and the second source feature, the first gate structure is between the first source feature and the common drain feature, and the second gate structure is between the common drain feature and the second source feature; forming a first source via connected to the first source feature; forming a second source via connected to the second source feature; forming a drain via connected to the common drain feature; forming a first gate via and a second gate via, wherein the first gate via is connected to the respective gate stack of the first gate structure and the second gate via is connected to the respective gate stack of the second gate structure; and wherein: each of the first source via and the second source via has a first top surface area, the drain via has a second top surface area, and each of the first gate via and the second gate via has a third top surface area, the first top surface area is greater than the second top surface area and the second top surface area is greater than the third top surface area, and the first gate via is disposed directly over and overlaps the first semiconductor layers and the second gate via is disposed directly over an isolation region and does not overlap the second semiconductor layers.
Liaw teaches a semiconductor device, comprising: a substrate; a gate structure on the substrate extending along a gate direction, the gate structure having a gate stack and gate spacers along sidewalls of the gate stack; a source feature and a drain feature, wherein the gate structure is disposed between the source feature and the drain feature; semiconductor layers disposed between the source feature and the drain feature, wherein the gate structure wraps the semiconductor layers; a source via connected to the source feature; a drain via connected to the drain feature; a gate via connected to the gate stack; wherein the source via has a first top surface area, the drain via has a second top surface area, and the gate via has a third top surface area.
Liaw1 teaches the source via has a first top surface area, the drain via has a second top surface area, and the gate via has a third top surface area; wherein the first top surface area is greater than the second top surface area and the second top surface area is greater than the third top surface area.
Chen et al. (US 20150332962 A1; hereinafter Chen) teaches a semiconductor device comprising a gate via and a semiconductor layer, wherein the gate via does not overlap edges of the semiconductor layer.
However, the prior art fails to teach or reasonably suggest “ wherein each of the first source via and the second source via has a first top surface area, the drain via has a second top surface area, and each of the first gate via and the second gate via has a third top surface area; wherein the first top surface area is greater than the second top surface area and the second top surface area is greater than the third top surface area” together with all the limitations of claim 11 as claimed. Claims 12-15 are allowable insofar as they depend upon and require all the limitations of claim 11.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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