DETAILED ACTION
This office action is in response to the application filed on 7/22/2024. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
The present office action is made with all the suggested amendments being fully considered. Accordingly, claims 2-21 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/22/2024, 11/27/2024 and 1/7/2025 are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 2, 11, 14, 17, 20-21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang (US 2019/0067027)
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
With respect to Claim 2, Wang shows (Fig. 2-12) all aspects of the current invention including a method comprising:
forming a semiconductor fin (64A,64B) in a wafer (50)
forming a silicon layer (83) over the semiconductor fin;
forming an oxide layer (86) over the silicon layer
after the oxide layer is formed, forming a dielectric barrier layer (85) between the silicon layer and the oxide layer, wherein the dielectric barrier layer comprises silicon and nitrogen (see Fig 9 and par 41-43; layer 86 is annealed and further the top portion of the dielectric is oxidized which forms a dielectric barrier layer 85 and oxide layer 87)
forming a dielectric region (62) over the oxide layer and aside of the semiconductor fin
With respect to Claim 11, Wang shows (Fig. 1-14) all aspects of the current invention including a method comprising:
etching a semiconductor substrate (50) of a wafer to form trenches (61), wherein a semiconductor strip (fins 64A,64B) is located between the trenches
depositing a silicon layer (83) on sidewalls of the semiconductor strip
depositing an oxygen-containing dielectric layer (86) on the silicon layer
conducting nitrogen to penetrate through the oxygen-containing dielectric layer, wherein the nitrogen is blocked by the silicon layer to form a nitrogen-containing dielectric barrier layer (see Fig 9 and par 41-43; layer 86 is annealed and further the top portion of the dielectric is oxidized which forms a dielectric barrier layer 85 and oxygen-containing dielectric layer 87)
depositing a dielectric material on the oxygen-containing dielectric layer to form dielectric isolation regions (62);
recessing the dielectric isolation regions, wherein a top portion of the semiconductor strip higher than top surfaces of the dielectric isolation regions that has been recessed forms a semiconductor fin (64A,64B) (See Fig 10-11)
forming a gate stack (75A,75B) on the semiconductor fin;
forming source/drain regions (80) based on the semiconductor fin, wherein the source/drain regions are on opposite sides of the gate stack
With respect to Claim 14, Wang shows (Fig. 1-14) wherein the conducting the nitrogen comprises annealing the wafer in a nitrogen-containing gas.
With respect to Claim 17, Wang shows (Fig. 2-13) all aspects of the current invention including a method comprising:
forming a semiconductor strip (fins 64A,64B) as a surface part of a wafer (50)
depositing a silicon layer (83) on the semiconductor strip, wherein the silicon layer comprises horizontal portions on top surfaces of the wafer, and vertical portions on sidewalls of the semiconductor strip
depositing an oxide layer (86) on the silicon layer;
at a time after the oxide layer is deposited, forming a dielectric barrier layer between the silicon layer and the oxide layer, wherein the dielectric barrier layer comprises silicon and nitrogen (see Fig 9 and par 41-43; layer 86 is annealed and further the top portion of the dielectric is oxidized which forms a dielectric barrier layer 85 and oxide layer 87)
With respect to Claim 20, Wang shows (Fig. 2-13) further comprising etching parts of the vertical portions of the silicon layer to reveal a top portion of the semiconductor strip.
With respect to Claim 21, Wang shows (Fig. 2-13) further comprising forming a gate stack (75A,75B) on the top portion of the semiconductor strip.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4, 7-10, 15, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2019/0067027) in view of Lee (US 2015/0028458)
With respect to Claim 3, Wang shows (Fig. 2-12) most aspects of the present application including wherein the forming the dielectric barrier layer comprises annealing the wafer. Furthermore, although Wang does not explicitly disclose forming the dielectric barrier layer comprises annealing the wafer in ammonia (NH3), Wang discloses a dielectric layer comprises silicon and nitrogen may be formed by annealing the wafer in ammonia (NH3).
Additionally, and in the same field of endeavor, Lee teaches (Fig. 6) a method comprising forming a semiconductor fin (25) in a wafer (21) and forming a dielectric barrier layer (21a) on the wafer, wherein the dielectric barrier layer comprises silicon and nitrogen and forming the dielectric barrier layer comprises annealing the wafer in ammonia (NH3) (par 63; layer 11a is formed in the same capacity as layer 21a). Lee teaches nitride layers are commonly used in the semiconductor manufacturing art as diffusion barrier layers and annealing using ammonia to form the nitride layers.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to the method step of forming the dielectric barrier layer comprises annealing the wafer in ammonia in the device of Wang because nitride layers are commonly used in the semiconductor manufacturing art as diffusion barrier layers and annealing using ammonia to form the nitride layers, as taught by Lee, and applying a known method step for its conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
With respect to Claim 4, Wang shows (Fig. 2-12) wherein the dielectric barrier layer 85 has a nitrogen concentration higher than nitrogen concentrations in the oxide layer 87 and the silicon layer 83.
With respect to Claim 7, Wang shows (Fig. 2-12) wherein the annealing is performed at a temperature in a range between about 500°C and about 7000C (par 42)
With respect to Claim 8, Lee teaches (Fig. 6) wherein the forming the dielectric barrier layer comprising exposing the oxide layer to ammonia, and the oxide layer separates the silicon layer from the ammonia.
With respect to Claim 9, Wang shows (Fig. 2-12) further comprising: removing portions of the silicon layer, the dielectric barrier layer, and the oxide layer from the semiconductor fin; forming a replacement gate dielectric (66) on the semiconductor fin; and depositing a replacement gate electrode (68) on the replacement gate dielectric (see fig 10-12)
With respect to Claim 10, Wang shows (Fig. 2-12) wherein after the dielectric barrier layer is formed, a portion of the silicon layer comprises elemental silicon.
With respect to Claim 15, Wang shows (Fig. 2-12) most aspects of the present application including wherein the forming the dielectric barrier layer comprises annealing the wafer. Furthermore, although Wang does not explicitly disclose wherein the conducting the nitrogen comprises annealing the wafer in ammonia, Wang discloses a dielectric layer comprises silicon and nitrogen may be formed by annealing the wafer in ammonia (NH3).
Additionally, and in the same field of endeavor, Lee teaches (Fig. 6) a method comprising forming a semiconductor fin (25) in a wafer (21) and forming a dielectric barrier layer (21a) on the wafer, wherein the dielectric barrier layer comprises silicon and nitrogen and forming the dielectric barrier layer comprises annealing the wafer in ammonia (NH3) (par 63; layer 11a is formed in the same capacity as layer 21a). Lee teaches nitride layers are commonly used in the semiconductor manufacturing art as diffusion barrier layers and annealing using ammonia to form the nitride layers.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to the method step of wherein the conducting the nitrogen comprises annealing the wafer in ammonia in the device of Wang because nitride layers are commonly used in the semiconductor manufacturing art as diffusion barrier layers and annealing using ammonia to form the nitride layers, as taught by Lee, and applying a known method step for its conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
With respect to Claim 18, Wang shows (Fig. 2-12) most aspects of the present application including wherein the forming the dielectric barrier layer comprises annealing the wafer. Furthermore, although Wang does not explicitly disclose wherein the forming the dielectric barrier layer comprises annealing the wafer in ammonia, so that nitrogen in the ammonia is diffused through the oxide layer and accumulated between the silicon layer and the oxide layer, Wang discloses a dielectric layer comprises silicon and nitrogen may be formed by annealing the wafer in ammonia (NH3).
Additionally, and in the same field of endeavor, Lee teaches (Fig. 6) a method comprising forming a semiconductor fin (25) in a wafer (21) and forming a dielectric barrier layer (21a) on the wafer, wherein the dielectric barrier layer comprises silicon and nitrogen and forming the dielectric barrier layer comprises annealing the wafer in ammonia (NH3) (par 63; layer 11a is formed in the same capacity as layer 21a). Lee teaches nitride layers are commonly used in the semiconductor manufacturing art as diffusion barrier layers and annealing using ammonia to form the nitride layers.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to the method step of wherein the forming the dielectric barrier layer comprises annealing the wafer in ammonia, so that nitrogen in the ammonia is diffused through the oxide layer and accumulated between the silicon layer and the oxide layer in the device of Wang because nitride layers are commonly used in the semiconductor manufacturing art as diffusion barrier layers and annealing using ammonia to form the nitride layers, as taught by Lee, and applying a known method step for its conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2019/0067027) in view of Hsiao (US 2018/0166327).
With respect to Claim 12, Wang shows (Fig. 2-12) most aspects of the present application including a silicon layer on sidewalls of the semiconductor strip. However, Wang does not disclose wherein the silicon layer is deposited as a crystalline layer.
On the other hand, and in the same field of endeavor, Hsiao teaches (Fig. 6) a method comprising forming a semiconductor fin (102) in a wafer (101) and forming a silicon layer (140) on the fin, wherein the silicon layer is deposited as a crystalline layer (par 58). Hsiao teaches silicon layer being deposited as a crystalline layer is a material suitable for FINFET manufacturing of wafer material and deposition of layers.
Accordingly, , it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to the method step of wherein the silicon layer is deposited as a crystalline layer in the device of Wang, because silicon layer being deposited as a crystalline layer is a material suitable for FINFET manufacturing of wafer material and deposition of layers, as taught by Hsiao and selecting a known material based on its suitability for its intended use would have been obvious to the skilled artisan. See, Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
With respect to Claim 13, Wang shows (Fig. 2-12) most aspects of the present application including a silicon layer on sidewalls of the semiconductor strip. However, Wang does not disclose wherein the silicon layer is deposited as a polycrystalline layer.
On the other hand, and in the same field of endeavor, Hsiao teaches (Fig. 6) a method comprising forming a semiconductor fin (102) in a wafer (101) and forming a silicon layer (140) on the fin, wherein the silicon layer is deposited as a polycrystalline layer (par 58). Hsiao teaches silicon layer being deposited as a polycrystalline layer is a material suitable for FINFET manufacturing of wafer material and deposition of layers.
Accordingly, , it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to the method step of wherein the silicon layer is deposited as a polycrystalline layer in the device of Wang, because silicon layer being deposited as a polycrystalline layer is a material suitable for FINFET manufacturing of wafer material and deposition of layers, as taught by Hsiao and selecting a known material based on its suitability for its intended use would have been obvious to the skilled artisan. See, Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Allowable Subject Matter
Claims 5-6, 16 and 18 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/Q. B./
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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