DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim(s) 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 16, 20 of U.S. Patent No. 11335638, in view of He (USPGPUB DOCUMENT: 2017/0330832, hereinafter He).
Re claim 1 claim(s) 16 of U.S. Patent No. 11335638 teaches a structure, comprising: a first dielectric layer on a substrate; a second dielectric layer on the etch stop layer and comprising first and second interconnect structures connected to the first and second metal contacts, respectively; and an air gap between the first and second interconnect structures and enclosed by a third dielectric layer.
US Patent No. 11804439 does not teach comprising first and second metal contacts; an etch stop layer on the first dielectric layer;
Ting discloses first and second metal contacts(S/D/Gate of 116); an etch stop layer(126) on the first dielectric layer(110);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of He to the teachings of US Patent No. 11804439 in order to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches [Abstract, He]
Re claim 2 US Patent No. 11804439 and He disclose the structure of claim 1, wherein the first dielectric layer further comprises an electrode in the first dielectric layer and under the air-gap[US Patent No. 11804439].
Re claim 3 US Patent No. 11804439 and He disclose the structure of claim 1, further comprising a gate structure below the air gap and above a channel region in the substrate[US Patent No. 11804439].
Re claim 4 US Patent No. 11804439 and He disclose the structure of claim 3, further comprising a fourth dielectric layer above the gate structure and below the air gap[US Patent No. 11804439].
Re claim 5 US Patent No. 11804439 and He disclose the structure of claim 4, wherein the fourth dielectric layer comprises silicon nitride[US Patent No. 11804439].
Re claim 6 US Patent No. 11804439 and He disclose the structure of claim 1, wherein the first and second metal contacts are in contact with first and second source/drain regions in the substrate[US Patent No. 11804439].
Re claim 7 US Patent No. 11804439 and He disclose the structure of claim 1, wherein the air gap occupies from about 30% to about 70% of a space between the first and second metal contacts[US Patent No. 11804439].
Re claim 8 US Patent No. 11804439 and He disclose the structure of claim 1, wherein the third dielectric layer is in contact with a side surface of the etch stop layer[US Patent No. 11804439].
Re claim 9 claim(s) 16, 20 of U.S. Patent No. 11335638 teaches a structure, comprising: a first dielectric layer on a substrate; a second dielectric layer on the first dielectric layer; first interconnect structures through the second dielectric layer; and a third dielectric layer in the first and second dielectric layers and enclosing an air gap between the first and second metal lines.
US Patent No. 11804439 does not teach second interconnect structures
Ting discloses second interconnect structures(104/130)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of He to the teachings of US Patent No. 11804439 in order to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches [Abstract, He]
Re claim 10 US Patent No. 11804439 and He disclose the structure of claim 9, wherein the air gap extends into the first dielectric layer[US Patent No. 11804439].
Re claim 11 US Patent No. 11804439 and He disclose the structure of claim 9, wherein the first and second interconnect structures are in contact with first and second metal contacts through the first dielectric layer[US Patent No. 11804439].
Re claim 12 US Patent No. 11804439 and He disclose the structure of claim 9, further comprising an etch stop layer above the second dielectric layer, wherein the air gap extends through the etch stop layer[US Patent No. 11804439].
Re claim 13 US Patent No. 11804439 and He disclose the structure of claim 12, further comprising a fourth dielectric layer on the etch stop layer, wherein the air gap extends through the fourth dielectric layer[US Patent No. 11804439].
Re claim 14 US Patent No. 11804439 and He disclose the structure of claim 9, wherein the air gap occupies from about 40% to about 90% of a space between the first and second interconnect structures[US Patent No. 11804439].
Re claim 15 claim(s) 16 of U.S. Patent No. 11335638 teaches a structure, comprising: a first dielectric layer on a substrate; a second dielectric layer on the first dielectric layer; an interconnect structure in the second dielectric layer; a third dielectric layer adjacent to the interconnect structure; and an air gap in the second dielectric layer and enclosed by the third dielectric layer.
US Patent No. 11804439 does not teach a metal contact(S/D/Gate of 116) in the first dielectric layer; an interconnect structure(104/130) in contact with the metal contact(S/D/Gate of 116);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of He to the teachings of US Patent No. 11804439 in order to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches [Abstract, He]
Re claim 16 US Patent No. 11804439 and He disclose the structure of claim 15, wherein the air gap extends into the first dielectric layer[US Patent No. 11804439].
Re claim 17 US Patent No. 11804439 and He disclose the structure of claim 15, further comprising an other interconnect structure in the first dielectric layer, wherein the air gap is directly above the other interconnect structure[US Patent No. 11804439].
Re claim 18 US Patent No. 11804439 and He disclose the structure of claim 15, wherein a vertical length of the air gap is greater than a thickness of the second dielectric layer[US Patent No. 11804439].
Re claim 19 US Patent No. 11804439 and He disclose the structure of claim 15, wherein an inner surface of the air gap is curved[US Patent No. 11804439].
Re claim 20 US Patent No. 11804439 and He disclose the structure of claim 15, wherein the air gap comprises a first cavity in the first dielectric layer and a second cavity in the second dielectric layer[US Patent No. 11804439].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Prosecution Insights