DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-7 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KOMUTA et al. (Pub. No.: US 2013/0250298 A1), hereinafter as KOMUTA.
Regarding claim 1, KOMUTA discloses a device in Figs. 11-12, comprising: a substrate (wafer 1) (see Fig. 11 and [0050]); at least two integrated circuit (IC) regions (at least two adjacent semiconductor element 10/10d) over the substrate (see Fig. 12 and [0050-0051]); and a group of alignment marks (at least two of alignment mark 11c) extending continuously from one of the at least two IC regions to another of the at least two IC region (see Fig. 12 and [0051-0053]).
Regarding claim 2, KOMUTA discloses the device of claim 1, wherein each of the at least two IC regions comprises a rectangular shape (see Figs. 11-12).
Regarding claim 4, KOMUTA discloses the device of claim 1, further comprising: a stitching zone (dashing line/dicing line region) at an interface of two adjacent ones of the at least two IC regions (see Fig. 12).
Regarding claim 5, KOMUTA discloses the device of claim 4, wherein each of the at least two IC regions comprises functional features (solder bump 13 and circuitry within semiconductor element 10/10d) and wherein the stitching zone is free of any functional features (no circuits in dashing line/dicing line region) (see Figs. 11-12 and [0049-0052]).
Regarding claim 6, KOMUTA discloses the device of claim 4, wherein the stitching zone comprises an alignment zone (the region of dashing line/dicing line having alignment marks 11c) (see Fig. 12).
Regarding claim 7, KOMUTA discloses the device of claim 6, wherein the alignment zone comprises inter-level overlay measurement patterns (alignment marks 11c) (see Fig. 12 and [0051]).
Regarding claim 16, KOMUTA discloses an integrated circuit device, in Figs. 11-12, comprising: a substrate (wafer 1) (see Fig. 11 and [0050]); a first integrated circuit (IC) region (top left semiconductor element 10/10d), a second IC region (top right
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semiconductor element 10/10d), a third IC region (bottom right semiconductor element 10/10d), and a fourth IC region (bottom left semiconductor element 10/10d) over the substrate (see annotated Fig. 12 above and [0050-0051]); a first group of alignment marks (one group of alignment marks 11c) extending continuously from the first IC region to the second IC region (see annotated Fig. 12 above and [0051-0053]); a second group of alignment marks (another one group of alignment marks 11c) extending continuously from the second IC region to the third IC region (see annotated Fig. 12 above and [0051-0053]); a third group of alignment marks (another one group of alignment marks 11c) extending continuously from the third IC region to the fourth IC region (see annotated Fig. 12 above and [0051-0053]); and a fourth group of alignment marks (another one group of alignment marks 11c) extending continuously from the fourth IC region to the first IC region (see annotated Fig. 12 above and [0051-0053]).
Regarding claim 17, KOMUTA discloses the integrated circuit device of claim 16, further comprising: a first stitching zone (dashing line/dicing line region between first IC region and second IC region) between the first IC region and the second IC region (see annotated Fig. 12 above); a second stitching zone (dashing line/dicing line region between second IC region and third IC region) between the second IC region and the third IC region (see annotated Fig. 12 above); a third stitching zone (dashing line/dicing line region between third IC region and fourth IC region) between the third IC region and the fourth IC region (see annotated Fig. 12 above); and a fourth stitching zone (dashing line/dicing line region between first IC region and fourth IC region) between the first IC region and the fourth IC region (see annotated Fig. 12 above);
Regarding claim 18, KOMUTA discloses the integrated circuit device of claim 17, wherein each of the first IC region, the second IC region, the third IC region, and the fourth IC region comprise functional features (solder bump 13 and circuitry within semiconductor element 10/10d) and wherein the first stitching zone, the second stitching zone, the third stitching zone, and the fourth stitching zone are free of any functional features (no circuits in dashing line/dicing line region) (see Figs. 11-12 and [0049-0052]).
Regarding claim 19, KOMUTA discloses the integrated circuit device of claim 17, wherein the first stitching zone, the second stitching zone, the third stitching zone, and the fourth stitching zone form a cross shape with each of the first stitching zone, the second stitching zone, the third stitching zone, and the fourth stitching zone being an arm of the cross shape (see annotated Fig. 12 above).
Regarding claim 20, KOMUTA discloses the integrated circuit device of claim 17, wherein each of the first stitching zone, the second stitching zone, the third stitching zone, and the fourth stitching zone comprise inter-level overlay measurement patterns (some alignment marks 11c) and in-chip overlay measurement patterns (other alignment marks 11c) (see KOMUTA, see annotated Fig. 12 above and [0051]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over KOMUTA et al. (Pub. No.: US 2013/0250298 A1), hereinafter as KOMUTA, as applied to claim 1 above, and in view of FURUMIYA et al. (Pub. No.: US 2010/0164053 A1), hereinafter as FURUMIYA.
Regarding claim 3, KOMUTA discloses the device of claim 1, but fails to disclose further comprising: a plurality of conductive lines extending across two of the at least two IC regions.
FURUMIYA discloses a device in Fig. 1 comprising a substrate (wafer 11) at least two IC regions (two adjacent chip regions 14B) over the substrate (see [0045]), and wherein the device further comprising: seal rings (seal ring 13 and seal ring 17) and a plurality of conductive lines (connecting portion 15 and connection portion 18) extending across two of the at least two IC regions (see [0063-0065], [0074] and [0079-0082]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate seal rings and the plurality of conductive lines of the device of FURUMIYA into the device of KOMUTA for extending across two of the at least two IC regions because the modified device would have capability of performing testing of the circuit portion without requiring time-consuming effort and capability of contriving the effective utilization of the scribe region.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over KOMUTA et al. (Pub. No.: US 2013/0250298 A1), hereinafter as KOMUTA, as applied to claim 7 above, and in view of NING et al. (Pub. No.: US 2015/0278426 A1), hereinafter as NING.
Regarding claim 8, KOMUTA discloses the device of claim 7, but fails to wherein the inter-level overlay measurement patterns comprise box-in-box patterns, cross-in-cross patterns, parallel test lines, or abutting test lines.
NING discloses a device in Fig. 5B comprising a stitching zone (scribe area 550) comprising an alignment zone and wherein the alignment zone having inter-level overlay measurement patterns comprise box-in-box patterns (box-in-box patterns 580) (see [0034-0035] and [0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the alignment mark of the device of KOMUTA to have the box-in-box patterns as the alignment mark of the device of NING because is it well known to know box-in-box patterns for aligning mask patterning and wafer processing for effective result and lower manufacturing cost.
Claim 9-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over KOMUTA et al. (Pub. No.: US 2013/0250298 A1), hereinafter as KOMUTA in view of FURUMIYA et al. (Pub. No.: US 2010/0164053 A1), hereinafter as FURUMIYA.
Regarding claim 9, KOMUTA discloses an integrated circuit structure, in Figs. 11-12, comprising: a substrate (wafer 1) (see Fig. 11 and [0050]); at least two integrated circuit (IC) regions (at least two adjacent semiconductor element 10/10d) over the substrate (see Fig. 12 and [0050-0051]); a stitching zone (dashing line/dicing line region) at an interface of two adjacent ones of the at least two IC regions (see Fig. 12); at least one alignment mark (one alignment mark 11c) extending across the stitching zone (see Fig. 12 and [0051-0053]).
KOMUTA fails to disclose a plurality of conductive features across the stitching zone.
FURUMIYA discloses a device in Fig. 1 comprising a substrate (wafer 11) at least two IC regions (two adjacent chip regions 14B) over the substrate (see [0045]), and wherein the device further comprising: seal rings (seal ring 13 and seal ring 17) and a plurality of conductive lines (connecting portion 15 and connection portion 18) extending across two of the at least two IC regions (see [0063-0065], [0074] and [0079-0082]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate seal rings and the plurality of conductive lines of the device of FURUMIYA into the device of KOMUTA for extending across two of the at least two IC regions because the modified device would have capability of performing testing of the circuit portion without requiring time-consuming effort and capability of contriving the effective utilization of the scribe region.
Regarding claim 10, the combination of KOMUTA and FURUMIYA discloses the integrated circuit structure of claim 9, KOMUTA fails to disclose wherein the substrate comprises silicon, germanium, silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, soda-lime glass, fused silica, fused quartz, calcium fluoride (CaF2), or a combination thereof.
However, FURUMIYA discloses the substrate (wafer 11) comprises silicon (see [0050]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the material of silicon of the device of FURUMIYA for making the substrate of KOMUTA because it is well known to form semiconductor substrate from silicon for making reliable integrated circuit with low manufacturing cost.
Regarding claim 11, the combination of KOMUTA and FURUMIYA discloses the integrated circuit structure of claim 9, wherein each of the at least two IC regions comprises functional features (solder bump 13 and circuitry within semiconductor element 10/10d) and wherein the stitching zone is free of any functional features (no circuits in dashing line/dicing line region) (see Figs. 11-12 and [0049-0052]).
Regarding claim 12, the combination of KOMUTA and FURUMIYA discloses the integrated circuit structure of claim 9, wherein the stitching zone comprises inter-level overlay measurement patterns (alignment marks 11c) (see KOMUTA, Fig. 12 and [0051]).
Regarding claim 14, the combination of KOMUTA and FURUMIYA discloses the integrated circuit structure of claim 9, wherein the stitching zone comprises in-chip overlay measurement patterns (alignment marks 11c) (see KOMUTA, Fig. 12 and [0051]).
Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over KOMUTA et al. (Pub. No.: US 2013/0250298 A1), hereinafter as KOMUTA in view of FURUMIYA et al. (Pub. No.: US 2010/0164053 A1), hereinafter as FURUMIYA, as applied to claim 12 and 14 above, and in view of NING et al. (Pub. No.: US 2015/0278426 A1), hereinafter as NING.
Regarding claim 13, the combination of KOMUTA and FURUMIYA discloses the integrated circuit structure of claim 12, but fails to wherein the inter-level overlay measurement patterns comprise box-in-box patterns, cross-in-cross patterns, parallel test lines, or abutting test lines.
NING discloses a device in Fig. 5B comprising a stitching zone (scribe area 550) comprising an alignment zone and wherein the alignment zone having inter-level overlay measurement patterns comprise box-in-box patterns (box-in-box patterns 580) (see [0034-0035] and [0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the alignment mark of the device of KOMUTA to have the box-in-box patterns as the alignment mark of the device of NING because is it well known to know box-in-box patterns for aligning mask patterning and wafer processing for effective result and lower manufacturing cost.
Regarding claim 15, the combination of KOMUTA and FURUMIYA discloses the integrated circuit structure of claim 14, but fails to wherein the in-chip overlay measurement patterns comprise box-in-box patterns, cross-in-cross patterns, parallel test lines, or abutting test lines.
NING discloses a device in Fig. 5B comprising a stitching zone (scribe area 550) comprising an alignment zone and wherein the alignment zone having in-chip overlay measurement patterns comprise box-in-box patterns (box-in-box patterns 580) (see [0034-0035] and [0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the alignment mark of the device of KOMUTA to have the box-in-box patterns as the alignment mark of the device of NING because is it well known to know box-in-box patterns for aligning mask patterning and wafer processing for effective result and lower manufacturing cost.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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