DETAILED ACTION
This Office action responds to Applicant’s invention filed on 07/22/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-9.
Information Disclosure Statement (IDS)
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDSs have been considered.
Specification Objection
The specification has been checked to the extend necessary to determine the presence of possible minor errors. However, the Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over by Tung (US 2019/0006360) in view of Zang (US 2016/0225762).
Regarding claim 1, Tung shows (see, e.g., Tung: figs. 1-6) most aspects of a method for fabricating a semiconductor device, comprising:
Providing a substrate 12 having a fin-shaped structure
Forming a single diffusion break (SDB) structure 24/26 in the substrate 12 to divide the fin-shaped structure into a first portion and a second portion
Forming a first gate structure 36 on the SDB structure 24/26
Forming a second gate structure 38 adjacent to the first gate structure 36/42 on the fin-shaped structure
Forming an interlayer dielectric (ILD) layer 56 around the first gate structure 36
Transforming the first gate structure 72 into a first metal gate 70
However, Tung fails (see, e.g., Tung: figs. 1-6) to show a method step of removing the first metal gate 70 completely to form a first recess exposing a top surface of the SDB structure 24. Zang, in a similar method to Tung, shows (see, e.g., Zang: figs. 6A-6B, 7A-7B, and 8A-8B) the method step of removing the first metal gate 511 (see, e.g., Zang: par. [0029]) completely to form a first recess 701 exposing a top surface of the SDB structure 501 (see, e.g., Zang: par. [0029]). Zhang also shows (see, e.g., Zang: figs. 6A-6B, 7A-7B, and 8A-8B) that the method step of removing the first metal gate 511 completely to form a first recess 701 exposing a top surface of the SDB structure 501 is a part of the method of an isolation structure formation for a FinFET device with a SDB used to reduce the circuit area to enable the formation of high-density integrated circuits (see, e.g., Zang: par. [0001] – [0002]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of Zang of removing the first metal gate completely to form a first recess exposing a top surface of the SDB structure in the method of Tung in order to form an isolation structure formation for a FinFET device with a SDB used to reduce the circuit area to enable the formation of high-density integrated circuits.
Also, Tung in view of Zang shows (see, e.g., Zang: figs. 6A-6B, 7A-7B, and 8A-8B) that the methos comprises the step of:
Forming a dielectric layer 801 in the first recess 701
Regarding claim 7, Tung in view of Zang shows (see, e.g., Tung: figs. 1-6):
Forming the ILD layer 56 around the first gate structure 42 and the second gate structure 44
Transforming the first gate structure 42 and the second gate structure 44 into the first metal gate 72 and a second metal gate 74
Forming a cap layer 62 on each of the first metal gate 72 and the second metal gate 74
Removing the first metal gate to form the first recess (no label, see, e.g., Tung: fig. 6)
Forming a dielectric layer 80 in the first recess (no label, see, e.g., Tung: fig. 6)
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over by Tung in view of Zang in further view of Wang (US 2019/0386100).
Regarding claim 2, Tung in view of Zang shows (see, e.g., Tung: figs. 1-6, and see, e.g., Zang: figs. 6A-6B, 7A-7B, and 8A-8B) that:
Forming the ILD layer 56 around the first gate structure 36 and the second gate structure 38
Transforming the first gate structure 72 and the second gate structure 74 into the first metal gate 70 and a second metal gate 70
Removing part of the second metal gate 513 to form a second recess 805 (see, e.g., Zang: figs. 8A-8B)
Removing the first metal gate 511 to form the first recess 701 (see, e.g., Zang: figs. 6A-6B, 7A-7B, and 8A-8B)
However, Tung in view of Zang fails (see, e.g., Tung: figs. 1-6, and see, e.g., Zang: figs. 6A-6B, 7A-7B, and 8A-8B) to show a method step of forming a cap layer in the first recess and the second recess. Wang, in a similar method to Tung in view of Zang, shows (see, e.g., Wang: fig. 4A-4C) the method step of forming a cap layer 270 in the first recess and the second recess. Wang also shows (see, e.g., Wang: fig. 4A-4C) that forming the cap layer 270 in the first recess and the second recess results in a structure that functions as a “capping” layer of the trenches (see, e.g., Wang: par. [0030]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of Wang of forming a cap layer in the first recess and the second recess in the method of Tung in view of Zang in order to form a resulting structure that functions as a “capping” layer of the trenches.
Also, Tung in view of Zang in view of Wang shows (see, e.g., Wang: fig. 4A-4C):
Forming the dielectric layer 280 in the first recess (see, e.g., Zang: figs. 6A-6B, 7A-7B, and 8A-8B)
Planarizing the dielectric layer 280 and the cap layer 270
Allowable Subject Matter
Claims 3-6, and 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for objecting to claim 3: The prior art of record neither anticipates nor renders obvious that a bottom surface of the first gate structure is lower than a bottom surface of the second gate structure.
The following is an examiner’s statement of reasons for objecting to claim 4: The prior art of record neither anticipates nor renders obvious that a bottom surface of the first recess is lower than a bottom surface of the second recess.
The following is an examiner’s statement of reasons for objecting to claim 5: The prior art of record neither anticipates nor renders obvious the step of removing the first metal gate and part of the first spacer to form the first recess.
The following is an examiner’s statement of reasons for objecting to claim 6: The prior art of record neither anticipates nor renders obvious that a top surface of the first spacer is lower than a top surface of the ILD layer.
The following is an examiner’s statement of reasons for objecting to claim 8: The prior art of record neither anticipates nor renders obvious the step of removing the first metal gate and part of the first spacer to form the first recess.
Claim 9 depends on the objected claim 8.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9 of the patent US 12,094,783 in view of Zang (US 2016/0225762).
Regarding claim 1, claim 1 of patent US 12,094,783 shows most aspects of the instant invention, except the step of forming a second gate structure adjacent to the first gate structure on the fin-shaped structure. Zang, on the other hand and in the same field of endeavor, teaches (see, e.g., Zang: figs. 6A-6B, 7A-7B, and 8A-8B) the method step of forming a second gate structure adjacent to the first gate structure 513 on the fin-shaped structure (see, e.g., Zang: par. [0029]). Zang also teaches that the method step of forming a second gate structure adjacent to the first gate structure on the fin-shaped structure that helps create source/drain (S/D) regions that are formed on the substrate at opposite sides of each of the second and third metal gates by forming a self-aligned contact (SAC) through the ILD down to the source/drain regions (see, e.g., Zang: par. [0010]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of forming a second gate structure adjacent to the first gate structure on the fin-shaped structure to helps create source/drain (S/D) regions that are formed on the substrate at opposite sides of each of the second metal gates by forming a self-aligned contact (SAC) through the ILD down to the source/drain regions.
Regarding claim 2, claim 2 of patent US 12,094,783 shows all aspects of claim 2 of the instant invention.
Regarding claim 3, claim 3 of patent US 12,094,783 shows all aspects of claim 3 of the instant invention.
Regarding claim 4, claim 3 of patent US 12,094,783 shows all aspects of claim 4 of the instant invention.
Regarding claim 5, claim 5 of patent US 12,094,783 shows all aspects of claim 5 of the instant invention.
Regarding claim 6, claim 6 of patent US 12,094,783 shows all aspects of claim 6 of the instant invention.
Regarding claim 7, claim 7 of patent US 12,094,783 shows all aspects of claim 7 of the instant invention.
Regarding claim 8, claim 8 of patent US 12,094,783 shows all aspects of claim 8 of the instant invention.
Regarding claim 9, claim 9 of patent US 12,094,783 shows all aspects of claim 9 of the instant invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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