DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7-10, and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koizumi et al. (US 20120119379 A1; hereinafter Koizumi).
Regarding claim 1, FIGS. 8-18 and 42 of Koizumi teach a method of forming a package structure, comprising: providing a carrier (18 ¶ [0092]) having a dielectric layer (50 ¶ [0064]) thereon (see FIG. 11), wherein the dielectric layer (50) has a die attach region (region of 50 directly below 20) and a peripheral region surrounding the die attach region (other region of 50, see FIG. 9); mounting a die (20) over the dielectric layer (50) within the die attach region (region of 50 directly below 20 ¶ [0064], see FIG. 11); forming a redistribution circuit structure (30-31, 41-46 ¶ [0064],[0069]-[0070],[0074]) over the dielectric layer (50, see FIG. 15), wherein the redistribution circuit structure (30-31, 41-46) comprises an insulating protrusion (protrusion between 20 and 41) formed in the peripheral region (other region of 50) and extending along a thickness direction of the die (thickness direction of 20, see FIG. 13), and a conductive structure (31, 41-43 ¶ [0069]-[0070]) encapsulating the insulating protrusion (protrusion between 20 and 41); releasing the carrier (18) to expose the dielectric layer (50, see FIGS. 11-12); patterning the dielectric layer (50) to form a plurality of openings (50x) in the peripheral region (other region of 50), wherein a portion of the conductive structure (e.g. 31) is exposed by the plurality of openings (50x ¶ [0081], see FIG. 16); respectively forming a plurality of barrier layers (52) in the plurality of openings (50x ¶ [0121], see FIG. 18); and respectively forming a plurality of conductive terminals (47) over the plurality of barrier layers (52 ¶ [0193]-[0194], see FIG. 42).
Regarding claim 2, Koizumi teaches the method of claim 1, wherein a material of the plurality of barrier layers (52, e.g. insulating materials ¶ [0122]) is different from a material of the conductive structure (31 and 41-43, e.g. conductive materials ¶ [0069]-[0070]) and a material of the plurality of conductive terminals (47, e.g. solder material ¶ [0076]).
Regarding claim 3, Koizumi teaches the method of claim 1, wherein the redistribution circuit structure (30-31, 41-46) comprises: a first redistribution conductive layer (41 ¶ [0070]) covering a sidewall of the insulating protrusion (sidewall of protrusion between 20 and 41 corresponding with 30y) to form a conductive through via (portion of 41 within 30y, see FIG. 13); a first inter-dielectric layer (44 ¶ [0070]) overlying the first redistribution conductive layer (41, see FIG. 14); and a second redistribution conductive layer (42 ¶ [0070]) overlying the first inter-dielectric layer (44), wherein the first inter-dielectric layer (44) comprises a plurality of contact openings (44x ¶ [0073]) that are offset from the conductive through via (portion of 41 within 30y, see FIG. 14), and a portion of the second redistribution conductive layer (42) is filled in the plurality of contact openings (44x) to electrically connect to the first redistribution conductive layer (41 ¶ [0073]).
Regarding claim 4, Koizumi teaches the method of claim 3, wherein the first redistribution conductive layer (41) further extends over a top surface of the insulating protrusion (protrusion between 20 and 41) to form a conductive layer (portion of 41 extending between 30y and 30x) on the conductive through via (30y, see FIG. 13).
Regarding claim 5, Koizumi teaches the method of claim 3, and FIG. 14 of Koizumi further teaches wherein the redistribution circuit structure (30-31, 41-46) further comprises a second inter-dielectric layer (45 ¶ [0070]) overlying the second redistribution conductive layer (42) and a third redistribution conductive layer (43 ¶ [0070]) overlying the second inter-dielectric layer (45).
Regarding claim 7, Koizumi teaches the method of claim 1, and FIG. 18 of Koizumi teaches wherein no barrier layer (52) is formed within the die attach region directly under the die (region of 50 directly below 20).
Regarding claim 8, Koizumi teaches the method of claim 1, and FIG. 14 of Koizumi further teaches wherein the redistribution circuit structure (30-31, 41-46) comprises: a first redistribution conductive layer (41 ¶ [0070]) encapsulating the insulating protrusion (protrusion between 41 and 20), wherein the first redistribution conductive layer (41) comprises a plurality of conductive through vias (portions of 41 within 30y ¶ [0072]), and each of the plurality of conductive through vias (portions of 41 within 30y) has a U-shaped cross-section (see FIG. 18); a first inter-dielectric layer (44 ¶ [0070]) overlying the first redistribution conductive layer (41); and a second redistribution conductive layer (42 ¶ [0070]) overlying the first inter-dielectric layer (44).
Regarding claim 9, Koizumi teaches the method of claim 8, and FIG. 42 of Koizumi further teaches further comprising: bonding the die (20 of 10G) to a package (10H) through the plurality of conductive terminals (47) to form an electrically connecting structure (¶ [0193]-[0194]), wherein each of the plurality of conductive terminals (47) is vertically disposed between a bottom horizontal portion of the U-shaped cross-section of a corresponding conductive through via (bottom horizontal portion of portion of 41 extending through 30 in 10G) and a top surface of the package in the peripheral region (top surface of 10H), and no conductive terminal (47) is within the die attach region directly under the die (region of 50 directly below 20).
Regarding claim 10, FIGS. 8-18 and 42 of Koizumi teach a method of forming a package structure, comprising: mounting a die (20) over a dielectric layer (50 ¶ [0064], see FIG. 9); forming an insulating encapsulation (30) to encapsulate the die (20 ¶ [0092], see FIG. 11); forming a redistribution circuit structure (31, 41-46) over the insulating encapsulation (30 ¶ [0064],[0069]-[0070],[0074]), the redistribution circuit structure (31, 41-46) comprising a redistribution conductive layer (31, 41), the redistribution conductive layer (31, 41) distributed in the insulating encapsulation (30) and extending from a first surface of the insulating encapsulation (top surface of 30) to a second surface of the insulating encapsulation (bottom surface of 30 ¶ [0096], see FIG. 13); patterning the dielectric layer (50) to expose portions of the redistribution conductive layer (31, 41) at the second surface of the insulating encapsulation (exposed portions of 31 at bottom surface of 31 ¶ [0138], see FIG. 16); forming a barrier layer (52) over the redistribution conductive layer exposed by the second surface of the insulating encapsulation (31 ¶ [0139]); and forming a conductive terminal (47) over the barrier layer (52 ¶ [0114], see FIG. 17), wherein no barrier layer (52) is formed in a region at a same level of the plurality of barrier layers directly under the die (region of 50 directly under 20, see FIG. 18).
Regarding claim 16, FIGS. 8-18 and 42 of Koizumi teach a method of forming a package structure, comprising: forming a die (20) in an insulating encapsulation (30 ¶ [0092], see FIG. 11); forming a redistribution circuit structure (31, 41-46) over the insulating encapsulation (30 ¶ [0064],[0069]-[0070],[0074], see FIG. 15), the redistribution circuit structure (31, 41-46) comprising a redistribution conductive layer (41), the redistribution conductive layer (41) distributed in the insulating encapsulation (30) and extending from a first surface of the insulating encapsulation (top surface of 30) to a second surface of the insulating encapsulation (bottom surface of 30); forming a conductive terminal (47 shown in FIG. 42) over the second surface of the insulating encapsulation (bottom surface of 30 ¶ [0114],[0194]), wherein no conductive terminal (47) is formed in a region at a same level of the conductive terminal directly under the die (region of 50 directly under 20, see FIGS. 18 and 42); and forming a barrier layer (52) between the redistribution conductive layer (41) and the conductive terminal (47 ¶ [0121]), wherein the barrier layer (52) has a top surface (top surface of 52) substantially level with the second surface of the insulating encapsulation (bottom surface of 30, see FIG. 18).
Regarding claim 17, Koizumi teaches the method of claim 16, and FIG. 12 of Koizumi further teaches wherein the insulating encapsulation (30) comprises a through hole (30y) extending from the first surface of the insulating encapsulation (top surface of 30) to the second surface of the insulating encapsulation (bottom surface of 30 ¶ [0072]).
Regarding claim 18, Koizumi teaches the method of claim 17, and FIGS. 13-14 and 18 of Koizumi further teach wherein the redistribution circuit structure (31, 41-46) comprises a first redistribution conductive layer (41 ¶ [0070]) on the first surface of the insulating encapsulation (top surface of 30), wherein a portion of the first redistribution conductive layer (portion of 41 within 30y) is filled in the through hole (30y) to form a conductive via with a U-shaped structure (portion of 41 within 30y, see FIG. 13); a first inter-dielectric layer (44) overlying the first redistribution conductive layer (41 ¶ [0070]), wherein the first inter-dielectric layer (44) comprises a protrusion (portion of 44 within 30y) protruding into the through hole (30y), so that the protrusion (portion of 44 within 30y) is laterally surrounded by the conductive via (portion of 41 within 30y, see FIG. 14); and a second redistribution conductive layer (42 ¶ [0070]) on the first inter-dielectric layer (44), wherein the first inter-dielectric layer (44) comprises a contact opening (44x ¶ [0073]) that is offset from the through hole (30y, see FIG. 18), and a portion of the second redistribution conductive layer (42) is filled in the contact opening (44x) to electrically connect the first redistribution conductive layer (41).
Regarding claim 19, Koizumi teaches the method of claim 18, and FIG. 14 of Koizumi further teaches wherein the redistribution circuit structure (31, 41-46) further comprises a second inter-dielectric layer (45 ¶ [0070]) overlying the second redistribution conductive layer (42) and a third redistribution conductive layer (43 ¶ [0070]) on the second inter-dielectric layer (45).
Regarding claim 20, Koizumi teaches the method of claim 16, and FIG. 18 of Koizumi further teaches wherein the insulating encapsulation (30) covers an active surface (surface of 22 and 23) and sidewalls of the die (sidewalls of 20).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 6, and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Koizumi in view of Geissler et al. (US 20180226377 A1; hereinafter Geissler).
Regarding claim 1, FIGS. 8-18 and 42 of Koizumi teach a method of forming a package structure, comprising: providing a carrier (18 ¶ [0092]) having a dielectric layer (50 ¶ [0064]) thereon (see FIG. 11), wherein the dielectric layer (50) has a die attach region (region of 50 directly below 20) and a peripheral region surrounding the die attach region (other region of 50, see FIG. 9); mounting a die (20) over the dielectric layer (50) within the die attach region (region of 50 directly below 20 ¶ [0064], see FIG. 11); forming a redistribution circuit structure (30-31, 41-46 ¶ [0064],[0069]-[0070],[0074]) over the dielectric layer (50, see FIG. 15), wherein the redistribution circuit structure (30-31, 41-46) comprises an insulating protrusion (protrusion between 20 and 41) formed in the peripheral region (other region of 50) and extending along a thickness direction of the die (thickness direction of 20, see FIG. 13), and a conductive structure (31, 41-43 ¶ [0069]-[0070]) encapsulating the insulating protrusion (protrusion between 20 and 41); releasing the carrier (18) to expose the dielectric layer (50, see FIGS. 11-12); patterning the dielectric layer (50) to form a plurality of openings (50x) in the peripheral region (other region of 50), wherein a portion of the conductive structure (e.g. 31) is exposed by the plurality of openings (50x ¶ [0081], see FIG. 16); and respectively forming a plurality of conductive terminals (47) in the plurality of openings (50x ¶ [0194], see FIG. 42).
Koizumi does not teach respectively forming a plurality of barrier layers in the plurality of openings; and respectively forming a plurality of conductive terminals over the plurality of barrier layers.
FIGS. 1 and 4 of Geissler teach a method of forming a barrier layer (108) in an opening of a solder resist layer (opening of 116 ¶ [0026]), the opening (opening of 116) exposing a copper pad (104 ¶ [0024]); and forming a conductive terminal (102) over the barrier layer (108 ¶ [0026]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming the package structure taught by Koizumi with the method of forming the barrier layer taught by Geissler for the purpose of suppressing copper diffusion (¶ [0010]) and reducing the likelihood of connection failure due to stress (¶ [0011]).
Regarding claim 6, Koizumi as modified teaches the method of claim 1, and Geissler further teaches wherein a material of the plurality of barrier layers (108) comprises an electroless metal comprising electroless Ni, electroless Au, electroless Pd, electroless Co, or a combination thereof (e.g. electroless nickel/electroless palladium/immersion gold ¶ [0010],[0026]).
Regarding claim 10, FIGS. 8-18 and 42 of Koizumi teach a method of forming a package structure, comprising: mounting a die (20) over a dielectric layer (50 ¶ [0064], see FIG. 9); forming an insulating encapsulation (30) to encapsulate the die (20 ¶ [0092], see FIG. 11); forming a redistribution circuit structure (31, 41-46) over the insulating encapsulation (30 ¶ [0064],[0069]-[0070],[0074]), the redistribution circuit structure (31, 41-46) comprising a redistribution conductive layer (31, 41), the redistribution conductive layer (31, 41) distributed in the insulating encapsulation (30) and extending from a first surface of the insulating encapsulation (top surface of 30) to a second surface of the insulating encapsulation (bottom surface of 30 ¶ [0096], see FIG. 13); patterning the dielectric layer (50) to expose portions of the redistribution conductive layer (31, 41) at the second surface of the insulating encapsulation (exposed portions of 31 at bottom surface of 31 ¶ [0138], see FIG. 16).
Koizumi does not teach forming a barrier layer over the redistribution conductive layer exposed by the second surface of the insulating encapsulation; and forming a conductive terminal over the barrier layer, wherein no barrier layer is formed in a region at a same level of the plurality of barrier layers directly under the die.
FIGS. 1 and 4 of Geissler teach a method of forming a barrier layer (108) in an opening of a solder resist layer (opening of 116 ¶ [0026]), the opening (opening of 116) exposing a copper pad (104 ¶ [0024]); and forming a conductive terminal (102) over the barrier layer (108 ¶ [0026]).
Thus, Koizumi in view of Geissler teach forming the barrier layer (108 of Geissler) over the redistribution conductive layer (31, 41 of Koizumi) exposed by the second surface of the insulating encapsulation (bottom surface of 30 of Koizumi); and forming a conductive terminal (47 of Koizumi/102 of Geissler) over the barrier layer (108 of Geissler), wherein no barrier layer (108 of Geissler) is formed in a region at a same level of the plurality of barrier layers (instances of 108 of Geissler) directly under the die (region of 50 directly under 20 of Koizumi).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming the package structure taught by Koizumi with the method of forming the barrier layer taught by Geissler for the purpose of suppressing copper diffusion (¶ [0010]) and reducing the likelihood of connection failure due to stress (¶ [0011]).
Regarding claim 11, Koizumi as modified teaches the method of claim 10, and Geissler further teaches wherein a method of forming the barrier (108) comprises an electroless plating method (¶ [0010],[0026]).
Regarding claim 12, Koizumi as modified teaches the method of claim 10, and Geissler further teaches the material of the barrier layer (material of 108) comprises a metal comprising Ni, Au, Pd, Co, or a combination thereof (e.g. electroless nickel/electroless palladium/immersion gold ¶ [0010],[0026]).
Thus, Koizumi in view of Geissler teaches wherein a material of the barrier layer (material of 108 of Geissler, e.g. electroless nickel/electroless palladium, immersion gold ¶ [0010],[0026]) is different from a material of the redistribution conductive layer (material of 41 of Koizumi, e.g. copper) and a material of the conductive terminal (material of 102, e.g. solder material).
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Koizumi in view of Geissler, and further in view of Shimizu et al. (US 20130328211 A1; hereinafter Shimizu)
Regarding claim 13, Koizumi as modified teaches the method of claim 10, and FIGS. 13-14 of Koizumi further teach wherein a method of forming the redistribution circuit structure (31, 41-46) comprises: forming a plurality of first contact openings (30x) and a plurality of through holes (30y) in the insulating encapsulation (30 ¶ [0072]), wherein an active surface of the die (22-23) is exposed by the first contact openings (30x) and the through holes (30y) extend from the first surface to the second surface the insulating encapsulation (e.g. from the top surface to the bottom surface of 30, see FIG. 13); filling the first contact openings (30x) with a plurality of first conductive patterns (portions of 41 within 30x, see FIG. 13); conformally forming a plurality of second conductive patterns (31, portions of 41 within 30y) in the through holes (30y), so that the second conductive patterns (31, portions of 41 within 30y) are formed as cup-shaped structures (see FIG. 13); and forming an inter-dielectric layer (44 ¶ [0070]) over the first conductive patterns (portions of 41 within 30x) and the second conductive patterns (31, portions of 41 within 30y, see FIG. 14), wherein the inter-dielectric layer (44) comprises a plurality of protrusions (portions of 44 within 30y) protruding into the through holes (30y), so that the plurality of protrusions (portions of 44 within 30y) are laterally surrounded by the second conductive patterns (31, portions of 41 within 30y).
Koizumi as modified does not teach forming the plurality of first contact openings and the plurality of through holes in the insulating encapsulation by a photolithography method.
FIGS. 3A-8C of Shimizu teach a method of forming a package structure including: forming a plurality of first contact openings (41X) in an insulating encapsulation (41) by a photolithography method (¶ [0076]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming the package structure taught by Koizumi with the photolithography method taught by Shimizu for the purpose of quickly forming contact openings with precision at low cost.
Regarding claim 14, Koizumi as modified teaches the method of claim 13, and FIG. 16 of Koizumi further teaches wherein a plurality of second contact openings (50x) are formed in the dielectric layer (50) after patterning the dielectric layer (50 ¶ [0081], see FIG. 16), bottom portions of the second conductive patterns (bottom portions of 31, 41 within 30y) respectively disposed in the through holes (30y) are exposed by the second contact openings (50x).
FIG. 1 of Geissler further teaches the barrier layers (108) are respectively disposed within the second contact openings (openings in 116) without extending out of the second contact openings (openings in 116).
Regarding claim 15, Koizumi as modified teaches the method of claim 13, and FIG. 13 of Koizumi further teaches wherein one of the first conductive patterns (portions of 41 within 30x) extends from a respective first contact opening (30x) to partially cover the first surface of the insulating encapsulation (surface of 30 corresponding with 30x), while one of the second conductive patterns (portions of 41 within 30y) extends from a respective through hole (30y) to connect the one of the first conductive patterns at the first surface of the insulating encapsulation (portions of 41 within 30x).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights