DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, and 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20150115416 (Costa et al) in view of US 20040232554 (Hirano et al).
Concerning claim 1, Costa discloses a fabricating method of a semiconductor structure. . . (Figs. 1-3 and 5), comprising: providing a first device wafer (10) comprising a conductive silicon layer (18), a silicon oxide layer (14) and a silicon substrate (12) ([0029]), wherein: a first transistor is disposed on a front side of the first device wafer (Fig. 1), wherein the front side is a top surface of the conductive silicon layer (Fig. 1), and the first transistor comprises: a first gate structure (20) disposed on the front side (Fig. 1), two first source/drain doping regions (24 and 28) embedded within the first device wafer at two sides of the first gate structure ([0029]), a channel region (18) disposed between the two first source/drain doping regions and embedded within the first device wafer (Fig. 1 and [0029]); a first interlayer dielectric (ILD 30) covering and contacting the front side (Fig. 1); providing a wafer bonding to the first interlayer dielectric ([0032], note that the a carrier wafer is disclosed as being attached to the polymeric layer 34 for stability and the examiner is relying on that configuration for rejection purposes); after bonding the wafer to the first interlayer dielectric, entirely removing the silicon substrate (Figs. 2-3 and [0033]) followed by forming a first via plug (44) and a second via plug (48) to penetrate the first device wafer (Fig. 3); after forming the first via plug and the second via plug, forming a first dummy metal structure (46) contacting a back side of the first device wafer (Fig. 5), and overlapping the channel region (Fig. 5), wherein an entirety of the first dummy metal structure is solid metal ([0034], note that the material of the dummy metal structure is disclosed as being a backside metal which is known in the art), and after entirely removing the silicon substrate, the back side of the first device wafer is a bottom surface of the silicon oxide layer (Fig. 5).
Costa does not explicitly disclose that the semiconductor structure is formed with a heat dissipation structure. However, Costa does disclose that the dummy metal structure is formed of a backside metal material. Hirano discloses a semiconductor structure with effective heat-radiation (Fig. 11) that includes the use of a backside metal (18) formed of aluminum or tungsten (Abstract) that has a higher thermal conductivity than that of the support substrate 10 (made of silicon) thus the higher heat-radiating effect can be obtained as compared with a case of letting off the heat generated in the transistor T1 to the support substrate 10. Therefore, a self-heating effect in the SOI device can be controlled ([0034]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the dummy metal structure of the backside metal material of Hirano because it is known in the art as a suitable backside material and has the added benefit of providing a heat dissipation advantage to the device structure.
Continuing to claim 2, Costa in view of Hirano discloses further comprising: during forming the first dummy metal structure, forming a second dummy metal structure (Costa 50) contacting the back side of the first device wafer, and overlapping one of the two first source/drain doping regions (Costa Fig. 5).
Considering claim 5, Costa in view of Hirano discloses wherein the wafer comprises a carrier wafer or a second device wafer (Costa [0032]).
Referring to claim 6, Costa in view of Hirano discloses forming a first transistor and that the second wafer can comprise a silicon wafer that is not subsequently removed (Costa [0032]).
Costa in view of Hirano as configured according to claim 5 does not disclose wherein the second device wafer comprises: a second transistor disposed on the second device wafer, wherein the second transistor comprises a second gate structure and two second source/drain doping regions; a second interlayer dielectric covering the second transistor; and a plurality of second metal interconnections disposed within the second interlayer dielectric, wherein the plurality of second metal interconnections respectively electrically connect to the two second source/drain doping regions. However, Hirano discloses another embodiment of s a semiconductor structure with effective heat-radiation (Fig. 23) in which the second substrate comprises the second device wafer comprises: a second transistor disposed on the second device wafer, wherein the second transistor comprises a second gate structure and two second source/drain doping regions; a second interlayer dielectric covering the second transistor; and a plurality of second metal interconnections disposed within the second interlayer dielectric, wherein the plurality of second metal interconnections respectively electrically connect to the two second source/drain doping regions (Fig. 23 and [0073]-[0076]). Hirano discloses that in such configuration a heat generated in the first chip can be radiated to the second chip (both of which contain the first and second transistors respectively) and a rise in temperature as the whole semiconductor device is controlled ([0073]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Costa to include the second transistor disposed on the second device wafer, wherein the second transistor comprises a second gate structure and two second source/drain doping regions; a second interlayer dielectric covering the second transistor; and a plurality of second metal interconnections disposed within the second interlayer dielectric, wherein the plurality of second metal interconnections respectively electrically connect to the two second source/drain doping regions and forming a more integrated device capable of effective heat dissipation.
Regarding claim 7, Costa in view of Hirano discloses further comprising a plurality of first metal interconnections (22 and 26) disposed within the first interlayer dielectric (Costa Fig. 1 and [0029]), wherein the plurality of first metal interconnections respectively electrically connect to the two first source/drain doping regions, and one of the plurality of second metal interconnections contacts one of the plurality of first metal interconnections (Costa Fig. 5 and Hirano Fig. 23 note that the first transistor and second transistor of Hirano are connected to one another through the metal interconnections).
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20150115416 (Costa et al) in view of US 20040232554 (Hirano et al) as applied to claim 1 above, and further in view of US 20170053882 (Jin et al).
Pertainnig to claim 3, Costa in view of Hirano discloses further comprising forming a . . . layer (Costa 58) covering and contacting the back side, wherein the second dummy metal structure is embedded within the . . . layer (Costa Fig. 5), and steps of forming the second dummy metal structure comprises: forming a third dummy metal layer (Costa 50) contacting the back side and overlapping one of the two first source/drain doping regions; forming a second metal plug (Costa vertical portion of feature 56 is being considered the metal plug) contacting the third dummy metal layer; and forming a fourth dummy metal layer (Costa horizontal portion of feature 56 is being considered the fourth dummy metal layer) contacting the second metal plug, wherein a top surface of the fourth dummy metal layer is exposed from the protective layer (Costa Fig. 5).
Costa in view of Hirano does not explicitly disclose that the layer is a protective layer. The layer of Costa is a backside redistribution layer, but the construction of this backside redistribution layer is not disclosed. However, Jin discloses a back redistribution layer that includes passivation layers, back insulating layers (which the examiner is interpreting to function as a protective layer), and conductive material layers ([0150]-[0152]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the backside redistribution layer of Costa with the passivation, insulating, and conductive layers (with the insulating layer functioning as a protective layer) because these materials are known to be suitable in the construction a redistribution layer structure.
As to claim 4, Costa in view of Hirano discloses further comprising forming a . . . layer (Costa 58) covering and contacting the back side, wherein the first dummy metal structure is embedded within the . . . layer (Costa Fig. 5), and steps of forming the first dummy metal structure comprises: forming a first dummy metal layer (Costa 46) contacting the back side and overlapping one of the two first source/drain doping regions; forming a first metal plug (Costa vertical portion of feature 54 is being considered the metal plug) contacting the first dummy metal layer; and forming a second dummy metal layer (Costa horizontal portion of feature 54 is being considered the fourth dummy metal layer) contacting the second metal plug, wherein a top surface of the fourth dummy metal layer is exposed from the protective layer (Costa Fig. 5).
Costa in view of Hirano does not explicitly disclose that the layer is a protective layer. The layer of Costa is a backside redistribution layer, but the construction of this backside redistribution layer is not disclosed. However, Jin discloses a back redistribution layer that includes passivation layers, back insulating layers (which the examiner is interpreting to function as a protective layer), and conductive material layers ([0150]-[0152]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the backside redistribution layer of Costa with the passivation, insulating, and conductive layers (with the insulating layer functioning as a protective layer) because these materials are known to be suitable in the construction a redistribution layer structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 10157838 discloses a method of forming a device on a silicon on insulator (SOI) substrate with backside contacts (Abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/ Examiner, Art Unit 2897 09/18/26
/CHAD M DICKE/ Supervisory Patent Examiner, Art Unit 2897
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