DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Joseph et al. (US 2015/0318182A1).
Joseph describes a method for making a semiconductor structure comprising: forming a liner structure 30 on an inner sidewall of a mask dielectric layer 20 overlying a substrate 10 (fig. 4C, 4D; para 46, 53, 54);
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200
400
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; forming a via hole in an area of the substrate exposed by the liner structure forming a tapering arc-shaped overhanging portion (fig. 4E);
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521
588
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; filing the via hole with a conductive material 50L (fig. 4I; para 72)
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.
With respect to claim 3, Joseph teaches planarizing the conductive material 50L using mask dielectric layer 20 as a stopping layer (para 73), which means the planarizing process would reach and polish the mask dielectric layer 20.
Claim(s) 13, 16 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Van Aelst et al. (US 2008/0050919A1).
With respect to claim 13, Van Aelst teaches a method for making a semiconductor substrate comprising: etching a dielectric SiO2 layer 2 overlying a semiconductor substrate 1 forming a pattern comprising an inner sidewall using fluorocarbon gas CF4 (para 226-235), the fluorocarbon gas CF4 would form a polymer attached to the sidewalls of the SiO2 layer 2 (please see Morikita et al. 2006/0219657A1 for description of active species of the CF4 gas forms polymer components attached to sidewalls during etching, para 48) or claimed a liner is formed on the inner sidewall during the etching; etching a portion of the substrate exposed by the liner to form a via hole through the substrate, wherein an undercut portion is formed at a top corner of the via hole (para 87, 131-139; fig. 4) or claimed recessing a portion of the semiconductor substrate exposed by the liner to form a via hole, wherein an undercut portion is formed at a top corner of the via hole; and forming a through substrate via in the via hole.
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589
956
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With respect to claim 16, Van Aelst teaches sequentially forming a passivation layer or insulating layer, a barrier, a seed conductive layer, and a conductive material in the via hole (para 5).
Morikita et al. 2006/0219657A1 is cited for description of active species of the CF4 gas forms polymer components attached to sidewalls during etching (para 48).
Allowable Subject Matter
Claims 2, 4-12, 14, 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 2, the closest applied prior art Joseph, even though teaches forming via hole having arc-shaped overhang portion (fig. 4E); however, Joseph doesn’t teach removing any of the overhang portion of the substrate before filling the via hole.
With respect to claim 4, and its dependent claims 5-7, the closest applied prior art Joseph, even though teaches forming via hole having arc-shaped overhang portion (fig. 4E); however, Joseph doesn’t teach wherein forming the liner structure on the inner sidewall of a dielectric layer comprises: etching the dielectric layer to form an opening of the dielectric layer, wherein the opening is defined by the inner sidewall of the dielectric layer, and a first liner of the liner structure is an etching by product grown on the inner sidewall of the dielectric layer.
With respect to claim 8, the closest applied prior art Joseph, even though teaches forming via hole having arc-shaped overhang portion (fig. 4E); however, Joseph doesn’t teach laterally thinning the liner structure when forming the via hole.
With respect to claim 9, and its dependent claims 10-12, the closest applied prior art Joseph, even though teaches forming via hole having arc-shaped overhang portion (fig. 4E); however, Joseph doesn’t teach further step of forming a conductive pattern layer of an interconnect structure over the dielectric layer, wherein the conductive pattern layer is electrically connected to the conductive material formed in the via hole. Joseph shows in fig 4L the conductive material formed in the via hole connected to another substrate, a transposer, or a packaging substrate through ball 70, which is away from the dielectric mask layer 20.
With respect to claim 14, the closest prior art Van Aelst doesn’t teach the undercut portion is a recess in which the portion of the semiconductor substrate is removed to leave an overhang portion of the semiconductor substrate overhanging the recess. He shows in fig. 1, the overhang portion is formed from the dielectric layer 2.
With respect to claim 15, the closest prior art Van Aelst doesn’t teach further step of trimming the semiconductor substrate after forming the via hole and before forming the through substrate via.
Claims 17-20 are allowed over the prior art because the closest applied prior art Joseph, even though teaches forming via hole having arc-shaped overhang portion (fig. 4E); however, Joseph doesn’t teach the arc-shape overhang or annular overhang is formed at a top edge of the substrate. Joseph shows in Fig. 4E the arc-shaped overhang is formed below the top edge of the substrate.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11594420 and over claims 1-20 of U.S. Patent No. 12142485. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims 1-20 of U.S. Patent 11594420 and claims 1-20 of U.S. Patent No. 12142485.describe the same steps, which encompass the claimed invention of forming via through a substrate, including forming a first and second protective films or liners on inner sidewalls of openings in a dielectric layer, the first liner is a byproduct from etching the dielectric layer; removing a portion of the substrate through the openings to form undercut or overhang portion at a top edge of the substrate; trimming to remove the overhang portion, the protective films/liners, and a portion of the dielectric layer; forming conductive pattern on the dielectric layer and the via to form interconnect structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY VU NGUYEN DEO whose telephone number is (571)272-1462. The examiner can normally be reached 9-5 M-F.
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/DUY VU N DEO/Primary Examiner, Art Unit 1713
6/1/2026
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