DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/23/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,125,798. Although the claims at issue are not identical, they are not patentably distinct from each other because applicant claims the method of making the device of US12125798 and broadens the claims by removing the limitation requiring a thermal conductivity of the electrical insulating and thermal conducive layer is substantially greater than a thermal conductivity of the dielectric structure.
A manufacturing method of a semiconductor device, comprising:
forming an electrical insulating and thermal conductive layer over a semiconductor substrate
forming a dielectric structure over the electrical insulating and thermal conductive layer
performing a damascene process over the dielectric structure to form an opening extending through the dielectric structure and the electrical insulating and thermal conductive layer
forming an electrical and thermal conductive layer over the dielectric structure, wherein the electrical and thermal conductive layer cover an inner surface of the opening
forming a circuit layer over the dielectric structure, wherein the circuit layer fills the rest of the opening
A semiconductor device, comprising:
a semiconductor substrate
an electrical insulating and thermal conductive layer disposed over the semiconductor substrate
an etch stop layer comprising silicon nitride and disposed between the semiconductor substrate and the electrical insulating and thermal conductive layer
a dielectric structure disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure
a circuit layer damascened in the dielectric structure, wherein the circuit layer comprises a bottom surface closest to the semiconductor substrate, and a lower surface of the etch stop layer is substantially coplanar with the bottom surface of the circuit layer
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,002,761. Although the claims at issue are not identical, they are not patentably distinct from each other because Although the claims at issue are not identical, they are not patentably distinct from each other because applicant claims the method of forming the semiconductor device of US12002761 and broadens the claims by removing limitations wherein a thermal conductivity of the electrical insulating layer and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure, and removing the limitation of a lower surface of the electrical insulating and thermal conductive layer is substantially coplanar with the bottom surface of the circuit layer.
A manufacturing method of a semiconductor device, comprising:
forming an electrical insulating and thermal conductive layer over a semiconductor substrate
forming a dielectric structure over the electrical insulating and thermal conductive layer
performing a damascene process over the dielectric structure to form an opening extending through the dielectric structure and the electrical insulating and thermal conductive layer
forming an electrical and thermal conductive layer over the dielectric structure, wherein the electrical and thermal conductive layer cover an inner surface of the opening
forming a circuit layer over the dielectric structure, wherein the circuit layer fills the rest of the opening
A semiconductor device, comprising:
a semiconductor substrate
an electrical insulating and thermal conductive layer disposed over the semiconductor substrate
a dielectric structure disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure
a circuit layer damascened in the dielectric structure, wherein the circuit layer comprises a bottom surface closest to the semiconductor substrate, and a lower surface of the electrical insulating and thermal conductive layer is substantially coplanar with the bottom surface of the circuit layer
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,456,256. Although the claims at issue are not identical, they are not patentably distinct from each other because applicant claims the method of forming the semiconductor device of US11456256 and broadens the claims by removing limitations wherein a thermal conductivity of the electrical insulating layer and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure, along with multiple dielectric structures.
A manufacturing method of a semiconductor device, comprising:
forming an electrical insulating and thermal conductive layer over a semiconductor substrate
forming a dielectric structure over the electrical insulating and thermal conductive layer
performing a damascene process over the dielectric structure to form an opening extending through the dielectric structure and the electrical insulating and thermal conductive layer
forming an electrical and thermal conductive layer over the dielectric structure, wherein the electrical and thermal conductive layer cover an inner surface of the opening
forming a circuit layer over the dielectric structure, wherein the circuit layer fills the rest of the opening
A semiconductor device, comprising:
a semiconductor substrate
an electrical insulating and thermal conductive layer disposed over the semiconductor substrate
a dielectric structure comprising a lower dielectric layer disposed over the electrical insulating and thermal conductive layer and an upper dielectric layer disposed over the lower dielectric layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure
a circuit layer disposed in the dielectric structure
an electrical insulating and thermal conductive interlayer disposed between the lower dielectric layer and the upper dielectric layer, wherein a thermal conductivity of the electrical insulating and thermal conductive interlayer is substantially greater than a thermal conductivity of the dielectric structure
Claim Objections
Claim 2 is objected to because of the following informalities: In line 1, applicant claims “…semiconductor device e as claimed…” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, 16-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lou (US Patent No. 6,265,307).
Regarding claim 1, Lou discloses a semiconductor device, comprising:
forming an electrical insulating and thermal conductive layer (204) disposed over the semiconductor substrate (200)
forming a dielectric structure (206) over the electrical insulating and thermal conductive layer (204)
performing a damascene process over the dielectric structure (206) to form an opening (228) through the dielectric structure (206) and electrical insulating and thermal conductive layer (204)
forming an electrical and thermal conductive layer (234) over the dielectric structure, wherein the electrical and thermal conductive layer cover an inner surface of the opening (230) (Figure 2I)
forming a circuit layer (234 upper) over the dielectric structure filling the rest of the opening (228)
Regarding claim 2, Lou discloses a material of the electrical insulating and thermal conductive layer comprises boron nitride (h-BN) or aluminum nitride (AlN) (col. 4, lines 40-51).
Regarding claim 3, Lou discloses an etch stop layer (206) disposed over the electrical insulating and thermal conductive layer (204), wherein the thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the etch stop layer (col. 7, lines 39-45).
Regarding claim 2, Lou discloses forming an etch stop layer (202) over the semiconductor substrate before the electrical insulating and thermal conductive layer is formed.
Regarding claim 3, Lou discloses forming an etch stop layer (206) over the semiconductor substrate after the electrical insulating and thermal conductive layer is formed.
Regarding claim 4, Lou discloses a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure (col. 7, lines 39-45)
Regarding claim 5, Lou discloses an electrical and thermal conductive layer (204) covering a surface of the circuit layer (234a/200) that is embedded in the dielectric structure (206), wherein a thermal conductivity of the electrical and thermal conductive layer is substantially greater than a thermal conductivity of the circuit layer (col. 2, lines 12-20; col. 4, lines 5-9).
Regarding claim 6, Lou discloses forming a seed layer (232) over the dielectric structure before the circuit layer is formed (Figure 2I).
Regarding claim 7, Lou discloses forming the seed layer (232) is formed after the electrical and thermal conductive layer (204) is formed (Figure 2I).
Regarding claim 8, Lou discloses forming a barrier layer (208) over the dielectric structure before the circuit layer is formed (Figure 2I).
Regarding claim 9, Lou discloses the barrier layer (208) is formed before the electrical and thermal conductive layer (204) is formed.
Regarding claim 16, Lou discloses a manufacturing method of a semiconductor device, comprising:
forming a lower dielectric layer (202) over the semiconductor substrate (200)
forming an electrical insulating and thermal conductive interlayer (204) over the lower dielectric layer (202)
forming an upper dielectric layer (206) over the lower dielectric layer (202)
forming a damascene opening (228) in the dielectric structure, wherein the damascene opening extends through the upper dielectric layer (206), the electrical insulating and thermal conductive interlayer (204), and the lower dielectric layer (202)
forming a circuit layer (234) to fill the damascene opening
Regarding claim 17, Lou discloses forming a via opening (228) extending through the upper dielectric layer (206), the electrical insulating and thermal conductive interlayer (204), and the lower dielectric layer (202); and forming a trench opening extending through the upper dielectric layer (206) and connecting the via opening (Figure 2H).
Regarding claim 18, Lou discloses forming an electrical insulating and thermal conductive interlayer (204) before the upper dielectric layer (206) is formed, wherein the opening extends through the upper dielectric layer (206), the electrical insulating and thermal conductive interlayer (204), the lower dielectric layer (202), and the electrical insulating and thermal conductive layer (204).
Regarding claim 20, Lou discloses forming an electrical and thermal conductive layer (204) over the lower dielectric layer (202) and the upper dielectric layer (206) before the circuit layer (234) is formed, wherein the electrical and thermal conductive layer covers an inner surface of the damascene opening (Figure 2I).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lou (US Patent No. 6,265,307) in view of Chang et al. (US Publication No. 2016/0365271).
Regarding claim 19, Lou discloses the limitations as discussed in the rejection of claim 16 above. Lou does not disclose forming an etch stop layer over the semiconductor substrate before the lower dielectric layer is formed. However, Chang discloses forming an etch stop layer (110) before a lower dielectric (130). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the method of Lou to include forming an etch stop layer, as taught by Chang, since it protect underlying layers and improves adhesion for subsequent layers (paragraph 26).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/N.R.P/ 9/20/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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