DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/23/2024 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 6, 9, 16 and 19 is rejected under 35 U.S.C. 102(a)(2) as being antcipated by Kabir (US 2022/0192042).
Regarding claim 1, Kabir teaches an integrated circuit package in fig. 7B, comprising:
a first semiconductor die (102-1), comprising:
a plurality of first bonding pads (see notation below)) disposed over a substrate (see notation below); and
a plurality of first vias (refer to 143 and center conductive vias in fig. 7B) disposed between the substrate and the first bonding pads, and connected to the first bonding pads (refer to the center conductive vias connecting to bonding pads), respectively, wherein a height of a first one of the first vias (refer to one of the center conductive vias) is greater than a height of a second one of the first vias (refer to the conductive via 143).
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Regarding claim 2, Kabir teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Kabir teaches the first semiconductor die (102-1) further comprises a plurality of first die pads disposed between the substrate and the first vias, the first one of the first vias (refer to one of the center conductive vias) is connected to a first one of the first die pads, and the second one of the first vias (refer to 143) is separated from a second one of the first die pads (see notation below).
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Regarding claim 6, Kabir teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Kabir teaches a second semiconductor die (102-2) bonded to the first semiconductor die (102-1) and comprising: a plurality of second bonding pads connected to the first bonding pads, respectively (see notation below).
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Regarding claim 9, Kabir teaches an integrated circuit package in fig. 7B, comprising:
a first semiconductor die (102-1), comprising: a plurality of first die pads (see notation below) disposed over a substrate; a plurality of first vias (refer to 143 and center conductive vias as labelled below) disposed over and connected to the first die pads (refer to center conductive vias connected to the die pads in the notation below); and
a plurality of first bonding pads (see notation below) disposed over the first vias, wherein a height of a first one of the first vias is greater than a height of a second one of the first vias.
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Regarding claim 16, Kabir teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Kabir teaches a second semiconductor die (refer to 102-2) bonded to the first semiconductor die (refer to102-1) and comprising: a plurality of second bonding pads connected to the first bonding pads, respectively (see notation below).
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Regarding claim 19, Kabir teaches a method of forming an integrated circuit package in fig. 7B, comprising:
forming first die pads over a first substrate;
forming first vias (143 and center conductive vias) over the first die pads, wherein a height of a first one of the first vias (refer to one of the center conductive vias) is greater than a height of a second one of the first vias (refer to 143); and
forming first bonding pads over the first vias (see notation below).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kabir (US 2022/0192042) as applied to claim 1 above, and further in view of Chen (US 2018/0005940).
Regarding claim 7, Kabir teaches all the limitations of the claimed invention for the same reasons as set forth above except for the first semiconductor die is bonded to the second semiconductor die through a face-to-face bonding.
Chen teaches the same field of endeavor wherein the first semiconductor die is bonded to the second semiconductor die through a face-to-face bonding (see fig. 2 and par. 31).
Thus it would have been obvious to one having ordinary skills in the art before the invention was made to include the first semiconductor die is bonded to the second semiconductor die through a face-to-face bonding as taught by Chen in the teaching of Kabir because face-to face bonding is commonly known in the art to bring the two chips’ interconnect layers a lot close together, enabling dense, short, low-power, high bandwidth chip to chip communication in a 3D structure.
Regarding claim 8, Kabir teaches all the limitations of the claimed invention for the same reasons as set forth above except for the first semiconductor die is bonded to the second semiconductor die through a face-to-back bonding.
Chen teaches the same field of endeavor wherein the first semiconductor die is bonded to the second semiconductor die through a face-to-back bonding (see fig. 3 and par. 32).
Thus it would have been obvious to one having ordinary skills in the art before the invention was made to include the first semiconductor die is bonded to the second semiconductor die through a face-to-back bonding as taught by Chen in the teaching of Kabir in order to vertically connect circuitry of the first die to the second die while preserving access to the other surface of the other die.
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kabir (US 2022/0192042) as applied to claim 9 above, and further in view of Chen (US 2018/0005940).
Regarding claim 7, Kabir teaches all the limitations of the claimed invention for the same reasons as set forth above except for the first semiconductor die is bonded to the second semiconductor die through a face-to-face bonding.
Chen teaches the same field of endeavor wherein the first semiconductor die is bonded to the second semiconductor die through a face-to-face bonding (see fig. 2 and par. 31).
Thus it would have been obvious to one having ordinary skills in the art before the invention was made to include the first semiconductor die is bonded to the second semiconductor die through a face-to-face bonding as taught by Chen in the teaching of Kabir because face-to face bonding is commonly known in the art to bring the two chips’ interconnect layers a lot close together, enabling dense, short, low-power, high bandwidth chip to chip communication in a 3D structure.
Regarding claim 8, Kabir teaches all the limitations of the claimed invention for the same reasons as set forth above except for the first semiconductor die is bonded to the second semiconductor die through a face-to-back bonding.
Chen teaches the same field of endeavor wherein the first semiconductor die is bonded to the second semiconductor die through a face-to-back bonding (see fig. 3 and par. 32).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the first semiconductor die is bonded to the second semiconductor die through a face-to-back bonding as taught by Chen in the teaching of Kabir in order to vertically connect circuitry of the first die to the second die while preserving access to the other surface of the other die.
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kabir (US 2022/0192042) as applied to claim 1 above, and further in view of Ho (US 2015/0194455).
Regarding claim 20, Kabir teaches all the limitations of the claimed invention for the same reasons as set forth above except for the first one of the first vias and the second one of the first vias are formed simultaneously.
Ho teaches the same field of an endeavor wherein the first one of the first vias (refer to via 130/132) and the second one of the first vias (refer to seal rings via 134A/134B) are formed simultaneously (see fig. 1D).
Thus, it would have been obvious to one having ordinary skills in the art at the time the invention was made to form the first one of the first vias and the second one of the first vias simultaneously as taught by Ho in the teaching of Kabir so that it simplifies the step of forming a vias by forming the vias simultaneously.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the first semiconductor die further comprises a first insulator between the second one of the first vias and the second one of the first die pads.” Claims 4-5 include all the limitations of claim 3.
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “a width of the first one of the first vias is less than a width of the second one of the first vias.”
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the first one of the first vias and the second one of the first vias are connected to the same first die pad.”
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the first one of the first vias and the second one of the first vias are connected to different first die pads.”
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “the first semiconductor die further comprises a first insulator between the second one of the first vias and the corresponding first bonding pad.” Claims 14-15 include all the limitations of claim 13.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818
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