Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“Semiconductor Arrangement Having Guard Ring Structures Surrounding a Vertical Conductive Structure and Methods of Forming the Same”
Because the suggested title reflects the guard ring structures, their positional relationship with the vertical conductive structure, and the corresponding methods of forming the semiconductor arrangement, thereby providing a more accurate and informative description of the invention.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Examiner conducted a comprehensive analysis of obviousness analysis including the Graham v. Deere analysis for each claim by (A) determining the scope and content of a reference claim relative to the claim in the application at issue; (B) determining the differences between the scope and content of the reference claim as determined in (A) and the claim in the application at issue; (C) determining the level of ordinary skill in the pertinent art; and (D) evaluation any objective indicia of nonobviousness.
The examiner has concluded that there is issue of double patenting rejection in the current application. This is because the claims in this application are deemed to be patentably does not distinct from any claims in a potential double patenting reference. Moreover, the examined application's claim is either anticipated or obvious over the reference claim(s).
Claims 1, 4-8, 12-14 and 16-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12113034 (hereinafter Pat-34). Although the claims at issue are not identical, they are not patentably distinct from each other:
Regarding claim 1. Claim 16 of Pat-34 recites a method for forming a semiconductor arrangement comprising:
forming a first guard ring in a first dielectric layer;
removing a portion of the first dielectric layer between a first surface of the first guard ring and a second surface of the first guard ring after forming the first guard ring to define an opening; and
forming a vertical conductive structure in the opening such that the first surface of the first guard ring is spaced apart from the second surface of the first guard ring by the vertical conductive structure.
Claim 1 of the instant application differs from the claim 16 of Pat-34 by expressly reciting:
"removing a first portion of a first dielectric layer to define a first closed-loop opening"
before
"forming a first guard ring in the first closed-loop opening."
However, this difference does not render claim 1 patentably distinct over claim 16 of Pat-34.
Claim 16 of Pat-34 requires formation of a first guard ring in a first dielectric layer, followed by removal of dielectric material from the region enclosed by the first guard ring to define an opening for receiving the vertical conductive structure. Accordingly, claim 16 already requires a guard ring embedded within the dielectric layer and surrounding the subsequently formed opening.
Although claim 16 of Pat-34 does not expressly recite first removing dielectric material to define a closed-loop opening prior to forming the first guard ring, a person of ordinary skill in the art would have found it obvious to first define a corresponding closed-loop opening in the dielectric layer before forming the guard ring therein. Performing such dielectric removal merely prepares the dielectric layer to receive the guard ring and represents an obvious intermediate fabrication step for carrying out the guard-ring formation expressly required by claim 16 of Pat-34.
The additional limitation of claim 1 therefore merely makes explicit an intermediate manufacturing step that would have been obvious to a person of ordinary skill in the art when implementing the method of claim 16 of Pat-34. This additional process step neither changes the structure of the resulting semiconductor arrangement nor alters the relationship between the first guard ring and the vertical conductive structure recited in claim 16 of Pat-34. Instead, it merely specifies one obvious manner of forming the guard ring already required by claim 16 of Pat-34.
Accordingly, the subject matter of claim 1 differs from claim 16 of Pat-34 only by the recitation of an obvious fabrication step that would have been performed in carrying out the method of claim 16 of Pat-34. Therefore, claim 1 does not define an invention that is patentably distinct from claim 16 of Pat-34 and is rejected under the judicially created doctrine of nonstatutory obviousness-type double patenting.
Regarding claim 4. The claim 16 of Pat-34 discloses the claim 1. Further, Claim 16 of Pat-34 recites a method comprising forming a first guard ring in a first dielectric layer, removing a portion of the first dielectric layer between a first surface and a second surface of the first guard ring to define an opening, and forming a vertical conductive structure in the opening.
Claim 17 of Pat-34 further recites:
removing a portion of a substrate overlying the first dielectric layer to further define the opening.
Thus, claims 16 and 17 of Pat-34 collectively require that, after the opening is formed within the first dielectric layer, the opening is extended beyond the first dielectric layer by continued material removal.
Claim 4 differs from claims 16 and 17 of Pat-34 by expressly reciting:
removing a first portion of a second dielectric layer under the first dielectric layer to further define the first closed-loop opening.
However, this additional limitation does not render claim 4 patentably distinct.
Claim 17 of Pat-34 already requires extending the opening beyond the first dielectric layer by removing underlying material. Although claim 17 of Pat-34 generically identifies the removed material as substrate material, it does not limit the opening-extension step to any particular material or prohibit the opening from extending through one or more dielectric layers located beneath the first dielectric layer.
A person of ordinary skill in the art would have found it obvious to identify the underlying material removed during the opening-extension step according to the particular layer structure of the semiconductor device. Thus, where the semiconductor device includes a second dielectric layer beneath the first dielectric layer, continuing the opening through that second dielectric layer merely represents implementation of the opening-extension process already required by claim 17 of Pat-34.
The recitation of removing a portion of the second dielectric layer therefore merely specifies the particular layer through which the opening is extended. Such specificity does not alter the purpose of the process step, namely extending the opening beyond the first dielectric layer, nor does it change the structure or function of the resulting semiconductor arrangement. Instead, it merely reflects the particular composition of the semiconductor layer stack through which the already-recited opening is formed.
Accordingly, expressly reciting removal of a second dielectric layer beneath the first dielectric layer while further defining the opening would have been an obvious variation of the method recited in claims 16 and 17 of Pat-34 and does not define an invention that is patentably distinct therefrom.
Therefore, claim 4 is rejected under the judicially created doctrine of nonstatutory obviousness-type double patenting.
Regarding claim 5. The claim 16 of Pat-34 discloses the claim 1. Further, Claim 16 of Pat-34 recites a method comprising forming a first guard ring in a first dielectric layer, removing a portion of the first dielectric layer between a first surface and a second surface of the first guard ring to define an opening, and forming a vertical conductive structure in the opening.
Claim 20 of Pat-34 further recites forming the vertical conductive structure such that the first guard ring is between the vertical conductive structure and a second guard ring formed in the first dielectric layer and spaced apart from the first guard ring. Thus, claims 16 and 20 of Pat-34 collectively require a semiconductor arrangement including a first guard ring and a second guard ring formed in the first dielectric layer, wherein the second guard ring is positioned outwardly of and spaced apart from the first guard ring.
Claim 5 differs from claims 16 and 20 of Pat-34 by expressly reciting:
removing a third portion of the first dielectric layer to define a second closed-loop opening; and forming a second guard ring in the second closed-loop opening.
However, these additional limitations do not render claim 5 patentably distinct.
Claim 20 of Pat-34 already requires formation of the second guard ring in the first dielectric layer. Although claim 20 of Pat-34 does not expressly recite the intermediate fabrication steps used to form the second guard ring, it likewise does not limit the particular manufacturing sequence by which the second guard ring is formed. A person of ordinary skill in the art would have found it obvious to first define a corresponding closed-loop opening in the first dielectric layer before forming the second guard ring therein, because defining the opening merely prepares the dielectric layer to receive the second guard ring required by claim 20 of Pat-34 and constitutes an obvious intermediate fabrication step for implementing the claimed guard-ring formation.
The recitation of removing a third portion of the first dielectric layer to define a second closed-loop opening merely specifies the manner in which the second guard ring is fabricated and does not alter the structural relationship already required by claim 20 of Pat-34, namely that the second guard ring is formed in the first dielectric layer and is spaced apart from the first guard ring. Nor does it change the function or operation of the resulting semiconductor arrangement. Instead, the additional limitation merely makes explicit an obvious implementation of the second guard-ring formation already recited in claim 20 of Pat-34.
Accordingly, modifying the method of claims 16 and 20 of Pat-34 to expressly recite removing a portion of the first dielectric layer to define a second closed-loop opening before forming the second guard ring would have been an obvious variation to a person of ordinary skill in the art and would not have resulted in a patentably distinct invention.
Therefore, claim 5 does not define an invention that is patentably distinct from the invention of claims 16 and 20 of Pat-34 and is rejected under the judicially created doctrine of nonstatutory obviousness-type double patenting.
Regarding claim 6. The claims 16 and 20 of Pat-34 discloses the claim 5. Further, Claim 16 of Pat-34 recites a method comprising forming a first guard ring in a first dielectric layer, removing a portion of the first dielectric layer between a first surface and a second surface of the first guard ring to define an opening, and forming a vertical conductive structure in the opening.
Claim 20 of Pat-34 further recites forming the vertical conductive structure such that the first guard ring is between the vertical conductive structure and a second guard ring formed in the first dielectric layer and spaced apart from the first guard ring. Thus, claims 16 and 20 of Pat-34 collectively require a semiconductor arrangement including a first guard ring and a second guard ring formed in the first dielectric layer, wherein the second guard ring is positioned outwardly of and spaced apart from the first guard ring.
Claim 6 differs from claims 16 and 20 of Pat-34 by expressly reciting:
"wherein forming the second guard ring comprises forming the second guard ring to surround the first guard ring on at least four sides."
However, this additional limitation does not render claim 6 patentably distinct.
Claim 20 of Pat-34 already requires formation of a second guard ring that is positioned outwardly of and spaced apart from the first guard ring. A person of ordinary skill in the art would have found it obvious to configure the second guard ring so as to laterally surround the first guard ring because a guard ring functions as a surrounding structure that provides electrical isolation or shielding around a protected region. Configuring the second guard ring to surround the first guard ring therefore merely represents an obvious geometric implementation of the outer guard-ring arrangement already required by claim 20 of Pat-34.
Furthermore, the recitation that the second guard ring surrounds the first guard ring "on at least four sides" merely specifies one obvious layout or geometric configuration of the second guard ring. This additional language neither changes the manner in which the second guard ring is formed nor alters the structural or functional relationship among the first guard ring, the second guard ring, and the vertical conductive structure already required by claims 16 and 20 of Pat-34. Rather, it merely describes one obvious configuration by which the second guard ring surrounds the first guard ring while remaining spaced apart therefrom.
Accordingly, modifying the method of claims 16 and 20 of Pat-34 to expressly configure the second guard ring to surround the first guard ring on at least four sides would have been an obvious variation to a person of ordinary skill in the art and would not have resulted in a patentably distinct invention.
Therefore, claim 6 does not define an invention that is patentably distinct from the invention of claims 16 and 20 of Pat-34 and is rejected under the judicially created doctrine of nonstatutory obviousness-type double patenting.
Regarding claim 7. The claims 16 and 20 of Pat-34 discloses the claim 5. Further, Claim 16 of Pat-34 recites a method comprising forming a first guard ring in a first dielectric layer, removing a portion of the first dielectric layer between a first surface and a second surface of the first guard ring to define an opening, and forming a vertical conductive structure in the opening.
Claim 20 of Pat-34 further recites forming the vertical conductive structure such that the first guard ring is between the vertical conductive structure and a second guard ring formed in the first dielectric layer and spaced apart from the first guard ring. Accordingly, claims 16 and 20 of Pat-34 require first and second guard rings formed in the same first dielectric layer and laterally spaced apart from one another.
Claim 7 differs from claims 16 and 20 of Pat-34 by expressly reciting:
"maintaining a fourth portion of the first dielectric layer between the first portion of the first dielectric layer and the third portion of the first dielectric layer such that the first guard ring is spaced apart from the second guard ring by the fourth portion of the first dielectric layer."
However, this additional limitation does not render claim 7 patentably distinct.
Claim 20 of Pat-34 already requires the first and second guard rings to be formed in the same first dielectric layer while remaining spaced apart from one another. In implementing this arrangement, the portions of the first dielectric layer removed to form the respective guard-ring openings are necessarily separated by a remaining portion of the first dielectric layer that maintains the spacing between the two guard rings. Thus, maintaining a portion of the first dielectric layer between the first and second guard rings merely represents an obvious implementation of the spaced guard-ring arrangement already required by claim 20 of Pat-34.
Furthermore, the recitation of maintaining a fourth portion of the first dielectric layer merely identifies the dielectric material intentionally left between the first and third removed portions during formation of the two guard-ring openings. This additional limitation neither changes the fabrication sequence nor alters the structural or functional relationship between the first guard ring and the second guard ring already required by claims 16 and 20 of Pat-34. Instead, it merely specifies the dielectric material by which the guard rings are maintained in the spaced-apart relationship recited in claim 20 of Pat-34.
Accordingly, expressly reciting maintenance of a portion of the first dielectric layer between the first and second guard rings would have been an obvious variation of the guard-ring arrangement already required by claim 20 of Pat-34 and would not have resulted in a patentably distinct invention.
Therefore, claim 7 does not define an invention that is patentably distinct from the invention of claims 16 and 20 of Pat-34 and is rejected under the judicially created doctrine of nonstatutory obviousness-type double patenting.
Regarding claim 8. The claim 16 of Pat-34 discloses the claim 1. Further, Claim 16 of Pat-34 recites a method comprising forming a first guard ring in a first dielectric layer, removing a portion of the first dielectric layer between a first surface and a second surface of the first guard ring to define an opening, and forming a vertical conductive structure in the opening.
Claim 8 differs from claim 16 of Pat-34 by expressly reciting:
"maintaining a third portion of the first dielectric layer between the first portion of the first dielectric layer and the second portion of the first dielectric layer such that the first guard ring is spaced apart from the vertical conductive structure by the third portion of the first dielectric layer."
However, this additional limitation does not render claim 8 patentably distinct.
As discussed with respect to claim 1, formation of the first guard ring would have obviously included first removing a portion of the first dielectric layer to define a closed-loop opening in which the first guard ring is subsequently formed. Claim 16 of Pat-34 further requires removing dielectric material within the first guard ring to define the opening for the vertical conductive structure. Thus, implementation of the method of claim 16 involves formation of separate openings for the first guard ring and the vertical conductive structure.
A person of ordinary skill in the art would have found it obvious to leave a portion of the first dielectric layer between these respective openings so that the first guard ring remains laterally spaced from the subsequently formed vertical conductive structure. Maintaining dielectric material between the guard-ring opening and the vertical-conductive-structure opening merely represents an obvious implementation of the fabrication process required to produce the guard-ring arrangement recited in claim 16 of Pat-34.
Furthermore, the recitation of maintaining a third portion of the first dielectric layer merely identifies the dielectric material intentionally left between the first and second removed portions of the first dielectric layer during formation of the respective openings. This additional limitation neither changes the fabrication sequence nor alters the structural or functional relationship between the first guard ring and the vertical conductive structure already required by claim 16 of Pat-34. Instead, it merely specifies the dielectric material by which the lateral spacing between the first guard ring and the vertical conductive structure is maintained.
Accordingly, expressly reciting maintenance of a third portion of the first dielectric layer between the first guard ring and the vertical conductive structure would have been an obvious variation of the method recited in claim 16 of Pat-34 and would not have resulted in a patentably distinct invention.
Therefore, claim 8 does not define an invention that is patentably distinct from the invention of claim 16 of Pat-34 and is rejected under the judicially created doctrine of nonstatutory obviousness-type double patenting.
Regarding claim 12. The claim 16 of Pat-34 discloses the claim 1. Further, Claim 16 of Pat-34 recites a method comprising forming a first guard ring in a first dielectric layer, removing a portion of the first dielectric layer between a first surface and a second surface of the first guard ring to define an opening, and forming a vertical conductive structure in the opening.
Claim 17 of Pat-34 further recites removing a portion of a substrate overlying the first dielectric layer to further define the opening. Thus, claims 16 and 17 of Pat-34 collectively require extending the opening beyond the first dielectric layer by removing substrate material.
Claim 12 differs from claims 16 and 17 of Pat-34 by expressly reciting:
"forming the first dielectric layer on a substrate; and removing a first portion of the substrate to further define the first closed-loop opening."
However, these additional limitations do not render claim 12 patentably distinct.
As discussed with respect to claim 1, formation of the first guard ring would have obviously included first removing a portion of the first dielectric layer to define a first closed-loop opening in which the first guard ring is subsequently formed. Once the first guard ring has been formed within the first closed-loop opening, a person of ordinary skill in the art would have found it obvious to continue that opening into the underlying substrate where additional opening depth is required. Such continuation of the first closed-loop opening merely represents implementation of the substrate-removal step already required by claim 17 of Pat-34.
Furthermore, the recitation of forming the first dielectric layer on a substrate merely identifies the substrate supporting the first dielectric layer from which material is subsequently removed. Likewise, the recitation of removing a first portion of the substrate to further define the first closed-loop opening merely specifies that the substrate-removal step follows the geometry of the previously formed closed-loop opening used to form the first guard ring. These additional limitations neither alter the fabrication sequence nor modify the structural relationship between the first guard ring and the subsequently formed vertical conductive structure. Rather, they merely describe an obvious continuation of the opening-extension process already required by claim 17 of Pat-34.
Accordingly, modifying the method of claims 16 and 17 of Pat-34 to expressly continue the first closed-loop opening into the substrate by removing a portion of the substrate would have been an obvious variation to a person of ordinary skill in the art and would not have resulted in a patentably distinct invention.
Therefore, claim 12 does not define an invention that is patentably distinct from the invention of claims 16 and 17 of Pat-34 and is rejected under the judicially created doctrine of nonstatutory obviousness-type double patenting.
Regarding claim 13. Claim 16 of Pat-34 recites a method for forming a semiconductor arrangement comprising:
Claim 16 of Pat-34 recites a method comprising forming a first guard ring in a first dielectric layer, removing a portion of the first dielectric layer between a first surface and a second surface of the first guard ring to define an opening, and forming a vertical conductive structure in the opening.
Claim 20 of Pat-34 further recites forming the vertical conductive structure such that the first guard ring is between the vertical conductive structure and a second guard ring formed in the first dielectric layer and spaced apart from the first guard ring. Accordingly, claims 16 and 20 of Pat-34 require a semiconductor arrangement including a first guard ring disposed between the vertical conductive structure and the second guard ring.
Claim 13 differs from claims 16 and 20 of Pat-34 by expressly reciting:
"removing a first portion of a first dielectric layer to define a first opening and a second portion of the first dielectric layer to define a second opening; forming a first guard ring in the first opening; forming a second guard ring in the second opening; removing a third portion of the first dielectric layer to define a third opening; and forming a vertical conductive structure in the third opening such that no line extending from the second guard ring intersects the vertical conductive structure without passing through the first guard ring."
However, these additional limitations do not render claim 13 patentably distinct.
As discussed with respect to claims 1 and 5, formation of the first and second guard rings would have obviously included first removing corresponding portions of the first dielectric layer to define respective openings in which the guard rings are subsequently formed. Likewise, formation of the vertical conductive structure would have obviously included removing dielectric material to define the opening in which the vertical conductive structure is subsequently formed. Accordingly, the recitation of separately defining the first, second, and third openings merely makes explicit intermediate fabrication steps for implementing the guard-ring and vertical-conductive-structure formation already required by claims 16 and 20 of Pat-34.
Furthermore, claim 20 of Pat-34 already requires the first guard ring to be positioned between the vertical conductive structure and the second guard ring. The additional limitation that "no line extending from the second guard ring intersects the vertical conductive structure without passing through the first guard ring" merely provides a geometric description of that same positional relationship. A person of ordinary skill in the art would have found it obvious to characterize the relative arrangement of the first guard ring, the second guard ring, and the vertical conductive structure in this manner because it merely describes one geometric implementation of the guard-ring arrangement already required by claim 20 of Pat-34 and does not define a different structural relationship.
The additional limitations therefore neither alter the fabrication sequence nor modify the structural or functional relationship among the first guard ring, the second guard ring, and the vertical conductive structure already required by claims 16 and 20. Instead, they merely make explicit obvious fabrication steps and describe the same guard-ring arrangement using different geometric terminology.
Accordingly, modifying the method of claims 16 and 20 of Pat-34 to expressly recite the formation of separate openings for the respective guard rings and the vertical conductive structure, and to characterize their relative positions as recited in claim 13, would have been an obvious variation to a person of ordinary skill in the art and would not have resulted in a patentably distinct invention.
Therefore, claim 13 does not define an invention that is patentably distinct from the invention of claims 16 and 20 of Pat-34 and is rejected under the judicially created doctrine of nonstatutory obviousness-type double patenting.
Regarding claim 14. The claims 16 and 20 of Pat-34 discloses the claim 13. Further, Claim 16 of Pat-34 recites a method comprising forming a first guard ring in a first dielectric layer, removing a portion of the first dielectric layer between a first surface and a second surface of the first guard ring to define an opening, and forming a vertical conductive structure in the opening.
Claim 20 of Pat-34 further recites forming the vertical conductive structure such that the first guard ring is between the vertical conductive structure and a second guard ring formed in the first dielectric layer and spaced apart from the first guard ring. Accordingly, claims 16 and 20 require a semiconductor arrangement in which the first guard ring is disposed around the region in which the vertical conductive structure is formed and is positioned between the vertical conductive structure and the second guard ring.
Claim 14 differs from claims 16 and 20 of Pat-34 by expressly reciting:
"wherein the vertical conductive structure is surrounded by the first guard ring on at least four sides."
However, this additional limitation does not render claim 14 patentably distinct.
Claim 16 of Pat-34 already requires the vertical conductive structure to be formed within the opening associated with the first guard ring, while claim 20 of Pat-34 further requires the first guard ring to be positioned between the vertical conductive structure and the second guard ring. A person of ordinary skill in the art would have found it obvious to configure the first guard ring so that it laterally surrounds the vertical conductive structure in implementing the guard-ring arrangement required by claims 16 and 20. Expressly reciting that the vertical conductive structure is surrounded by the first guard ring on at least four sides merely specifies one obvious geometric implementation of that guard-ring arrangement.
Furthermore, the recitation that the vertical conductive structure is surrounded by the first guard ring on at least four sides merely characterizes the layout of the first guard ring. This additional limitation neither changes the fabrication sequence nor alters the structural relationship among the first guard ring, the second guard ring, and the vertical conductive structure already required by claims 16 and 20 of Pat-34. Rather, it merely describes one obvious geometric configuration of the first guard ring while preserving the same positional relationship recited in the patented claims.
Accordingly, modifying the method of claims 16 and 20 of Pat-34 to expressly configure the first guard ring to surround the vertical conductive structure on at least four sides would have been an obvious variation to a person of ordinary skill in the art and would not have resulted in a patentably distinct invention.
Therefore, claim 14 does not define an invention that is patentably distinct from the invention of claims 16 and 20 of Pat-34 and is rejected under the judicially created doctrine of nonstatutory obviousness-type double patenting.
Regarding claim 16. The claims 16 and 20 of Pat-34 discloses the claim 13. Further, Claim 16 of Pat-34 recites a method comprising forming a first guard ring in a first dielectric layer, removing a portion of the first dielectric layer between a first surface and a second surface of the first guard ring to define an opening, and forming a vertical conductive structure in the opening.
Claim 20 of Pat-34 further recites forming the vertical conductive structure such that the first guard ring is between the vertical conductive structure and a second guard ring formed in the first dielectric layer and spaced apart from the first guard ring. Accordingly, claims 16 and 20 collectively require a semiconductor arrangement including first and second guard rings formed in the first dielectric layer, wherein the first guard ring is positioned between the vertical conductive structure and the second guard ring.
Claim 16 of the instant application differs from claims 16 and 20 of Pat-34 by expressly reciting:
"wherein at least one of the first guard ring or the second guard ring forms a closed-loop."
However, this additional limitation does not render the claimed invention patentably distinct.
Claims 16 and 20 of Pat-34 already require formation of first and second guard rings arranged relative to the vertical conductive structure in the manner recited therein. The additional limitation that at least one of the first guard ring or the second guard ring forms a closed-loop merely further defines the geometry of the guard-ring arrangement already required by claims 16 and 20 of Pat-34. This limitation does not modify the sequence of forming the guard rings, does not alter the positional relationship among the first guard ring, the second guard ring, and the vertical conductive structure, and does not result in a different semiconductor arrangement. Rather, it merely specifies a particular geometric implementation of the guard-ring arrangement already recited in the patented claims.
A person of ordinary skill in the art would have found it obvious to implement the guard-ring arrangement required by claims 16 and 20 of Pat-34 using a closed-loop guard ring because the closed-loop geometry simply defines the shape of the already-recited guard ring while preserving the positional relationship required by the patented claims. Accordingly, expressly reciting that at least one of the guard rings forms a closed-loop would have been an obvious variation that would not have resulted in a patentably distinct invention.
Therefore, claim 16 of the instant application does not define an invention that is patentably distinct from the invention of claims 16 and 20 of Pat-34 and is rejected under the judicially created doctrine of nonstatutory obviousness-type double patenting.
Regarding claim 17. Claim 1 of Pat-34 recites A semiconductor arrangement, comprising:
Claim 1 of Pat-34 recites a semiconductor arrangement comprising a first dielectric layer, a first guard ring in the first dielectric layer, a vertical conductive structure passing through the first dielectric layer, wherein the vertical conductive structure is surrounded by the first guard ring on at least four sides, and a conductive structure underlying the first guard ring and in contact with the vertical conductive structure.
Claim 17 of the instant application differs from Claim 1 of Pat-34 by expressly reciting:
"wherein the first guard ring defines a closed loop."
However, this additional limitation does not render the claimed invention patentably distinct.
Claim 1 of Pat-34 already requires a semiconductor arrangement including a first guard ring disposed in the first dielectric layer and surrounding the vertical conductive structure on at least four sides. The additional limitation that the first guard ring defines a closed loop merely further characterizes the geometry of the first guard ring already required by Claim 1 of Pat-34. Expressly identifying the first guard ring as defining a closed loop does not change the location of the first guard ring relative to the vertical conductive structure, does not alter the relationship between the first guard ring and the conductive structure underlying the first guard ring, and does not result in a different semiconductor arrangement. Rather, it merely provides a more specific geometric description of the guard-ring arrangement already recited in Claim 1 of Pat-34.
A person of ordinary skill in the art would have recognized that specifying the first guard ring as defining a closed loop merely identifies one geometric configuration of the guard ring while preserving the structural relationships already required by Claim 1 of Pat-34. Accordingly, expressly reciting that the first guard ring defines a closed loop would have been an obvious variation of the semiconductor arrangement recited in Claim 1 of Pat-34 and would not have resulted in a patentably distinct invention.
Therefore, claim 17 does not define an invention that is patentably distinct from Claim 1 of Pat-34 and is rejected under the judicially created doctrine of nonstatutory obviousness-type double patenting.
Regarding claim 18. The claim of Pat-34 discloses claim 17. Further, Claim 1 of Pat-34 recites a semiconductor arrangement comprising a first dielectric layer, a first guard ring in the first dielectric layer, a vertical conductive structure passing through the first dielectric layer, wherein the vertical conductive structure is surrounded by the first guard ring on at least four sides, and a conductive structure underlying the first guard ring and in contact with the vertical conductive structure.
Claim 18 of the instant application depends from claim 17 and further recites:
"wherein the conductive structure is in contact with the vertical conductive structure."
As discussed with respect to claim 17, the limitation that the first guard ring defines a closed loop merely further characterizes the geometry of the first guard ring already required by Claim 1 of Pat-34 and does not render the claimed semiconductor arrangement patentably distinct.
The additional limitation of claim 18, namely that the conductive structure is in contact with the vertical conductive structure, is expressly recited in Claim 1 of Pat-34. Accordingly, claim 18 does not add any structural relationship that distinguishes the claimed semiconductor arrangement from that recited in Claim 1 of Pat-34.
Viewed as a whole, claim 18 merely combines the guard-ring geometry addressed in claim 17 with the conductive-structure contact relationship already expressly required by Claim 1 of Pat-34. These limitations neither modify the structural relationship among the first guard ring, the vertical conductive structure, and the conductive structure nor result in a semiconductor arrangement that is patentably distinct from the arrangement recited in Claim 1 of Pat-34.
Accordingly, claim 18 does not define an invention that is patentably distinct from Claim 1 of Pat-34 and is rejected under the judicially created doctrine of nonstatutory obviousness-type double patenting.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-8, 13-14 and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. (US 20130154048).
Regarding claim 1. Lu discloses A method for forming a semiconductor arrangement, comprising:
removing a first portion of a first dielectric layer to define a first closed-loop opening, as illustrated in Figure 2, wherein openings are formed through first insulating layer 220 by photolithographically patterning a photoresist layer to expose selected portions of first insulating layer 220, followed by anisotropically etching the exposed portions of first insulating layer 220 (¶0018). The etched openings are configured to receive guard ring plugs 224 and correspond to the closed-loop guard ring configurations illustrated in Figures 5A-5D, thereby defining first closed-loop openings.
forming a first guard ring in the first closed-loop opening, as further illustrated in Figure 2, wherein conductive material is deposited into the etched openings and planarized to form guard ring plugs 224 in first insulating layer 220 (¶0019). Figures 5A-5D further illustrate that the guard ring defines a continuous closed loop surrounding an inner region.
removing a second portion of the first dielectric layer within an inner perimeter of the first guard ring to define an opening, as illustrated in Figure 3, wherein recesses are etched from the top surface of first insulating layer 220 into substrate 110 to form openings for through vias 330 (¶0020). Figure 3 illustrates that the through-via openings are formed within the inner perimeter of the previously formed guard ring 224.
forming a vertical conductive structure in the opening such that the vertical conductive structure is surrounded by the first guard ring on at least four sides, as further illustrated in Figure 3, wherein conductive material is deposited into the through-via openings to form through vias 330 (¶0020). Figures 5A-5D further illustrate that through via 330 is disposed within the inner region defined by the closed-loop guard ring, such that the through via is surrounded by the first guard ring on at least four sides.
Accordingly, Lu discloses each and every limitation of claim 1.
Regarding claim 5. Lu discloses The method of claim 1, As discussed above with respect to claim 1, Lu discloses removing portions of first insulating layer 220 by photolithographically patterning a photoresist layer and anisotropically etching the exposed portions of first insulating layer 220 to form openings for guard ring plugs 224 (Fig. 2; ¶0018). Lu further discloses depositing conductive material into the etched openings and planarizing the conductive material to form guard ring plugs 224, thereby forming guard rings in the first insulating layer (Fig. 2; ¶0019).
Claim 5 further recites:
"removing a third portion of the first dielectric layer to define a second closed-loop opening; and forming a second guard ring in the second closed-loop opening."
Lu expressly teaches these additional limitations in the embodiment illustrated in Figures 7A and 7B. Paragraph 0034 discloses that Figures 7A and 7B illustrate an embodiment including multiple guard rings comprising multiple guard ring plugs 224A-224D, and further teaches that processes similar to those discussed above with reference to Figures 1-4 are used, with the photolithographic masks modified to form the multiple guard ring plugs. Thus, Lu expressly teaches forming additional etched openings in first insulating layer 220 corresponding to additional guard ring plugs and subsequently filling those openings with conductive material to form additional guard rings.
Furthermore, Figure 7A illustrates that guard ring plugs 224A and 224C each form a solid closed-loop surrounding through via 330, and Figure 7B illustrates that these guard rings are formed in first insulating layer 220. Accordingly, Lu expressly teaches removing a third portion of the first dielectric layer to define a second closed-loop opening and forming a second guard ring in the second closed-loop opening.
Therefore, Lu discloses each and every limitation of claim 5.
Regarding claim 6. The method of claim 5, guard rings formed in first insulating layer 220 (Figs. 7A and 7B; ¶¶0034-0035). Specifically, paragraph 0034 teaches that the embodiment of Figures 7A and 7B provides multiple guard rings comprising multiple guard ring plugs 224A-224D, formed using processes similar to those described with respect to Figures 1-4.
Claim 6 further recites:
"wherein forming the second guard ring comprises forming the second guard ring to surround the first guard ring on at least four sides."
Lu expressly teaches this limitation. As illustrated in Figure 7A, guard ring 224A forms a first closed-loop guard ring surrounding through via 330, while guard ring 224C forms a second closed-loop guard ring surrounding guard ring 224A. Thus, guard ring 224C completely surrounds guard ring 224A, such that the second guard ring surrounds the first guard ring on at least four sides. Paragraph 0035 further teaches that guard ring plugs 224A and 224C each form solid shapes surrounding through via 330, consistent with the concentric guard-ring arrangement illustrated in Figure 7A.
Accordingly, Lu discloses each and every limitation of claim 6.
Regarding claim 7. The method of claim 5, As discussed above with respect to claim 5, Lu discloses an embodiment including multiple guard rings formed in first insulating layer 220 (Figs. 7A and 7B; ¶¶0034-0035). Specifically, paragraph 0034 teaches that the embodiment of Figures 7A and 7B provides multiple guard rings comprising guard ring plugs 224A-224D, formed using processes similar to those described with respect to Figures 1-4 by appropriately modifying the photolithographic masks.
Claim 7 further recites:
"maintaining a fourth portion of the first dielectric layer between the first portion of the first dielectric layer and the third portion of the first dielectric layer such that the first guard ring is spaced apart from the second guard ring by the fourth portion of the first dielectric layer."
Lu expressly teaches this limitation. As illustrated in Figure 7A, first guard ring 224A and second guard ring 224C are formed as separate, concentric closed-loop guard rings within first insulating layer 220. The openings used to form guard rings 224A and 224C are separated by an intervening portion of first insulating layer 220, such that guard ring 224A is spaced apart from guard ring 224C by the remaining dielectric material. Figure 7A further illustrates that guard ring plugs 224B and 224D are formed as broken guard rings in the intermediate region, as described in paragraph 0035, thereby confirming that portions of first insulating layer 220 remain between the first and second guard rings rather than being completely occupied by conductive guard ring material.
Accordingly, Lu expressly teaches maintaining a portion of the first dielectric layer between the portions removed to form the first and second guard rings, such that the first guard ring is spaced apart from the second guard ring by the remaining portion of the first dielectric layer, as claimed.
Therefore, Lu discloses each and every limitation of claim 7.
Regarding claim 8. The method of claim 1, As discussed above with respect to claim 1, Lu discloses removing portions of first insulating layer 220 to form openings for guard ring plugs 224 (Fig. 2; ¶0018), forming the guard ring plugs in the openings (Fig. 2; ¶0019), removing another portion of first insulating layer 220 within the guard ring to form an opening for through via 330 (Fig. 3; ¶0020), and forming through via 330 in the opening (Fig. 3; ¶0020).
Claim 8 further recites:
"maintaining a third portion of the first dielectric layer between the first portion of the first dielectric layer and the second portion of the first dielectric layer such that the first guard ring is spaced apart from the vertical conductive structure by the third portion of the first dielectric layer."
Lu expressly teaches this limitation. As illustrated in Figure 3, guard ring 224 is formed in first insulating layer 220, and through via 330 is subsequently formed within the inner perimeter of the guard ring. A portion of first insulating layer 220 remains between the opening used to form guard ring 224 and the opening used to form through via 330, thereby spacing the guard ring apart from the through via by the remaining dielectric material. Figures 5A-5D further illustrate that through via 330 is disposed within the inner region of the closed-loop guard ring while remaining spaced apart therefrom by the intervening portion of first insulating layer 220.
Accordingly, Lu expressly teaches maintaining a portion of the first dielectric layer between the portions removed to form the first guard ring and the vertical conductive structure, such that the first guard ring is spaced apart from the vertical conductive structure by the remaining portion of the first dielectric layer, as claimed.
Therefore, Lu discloses each and every limitation of claim 8.
Regarding claim 13. Lu discloses a method for forming a semiconductor arrangement comprising:
removing portions of first insulating layer 220 by photolithographically patterning a photoresist layer and anisotropically etching first insulating layer 220 to form openings for guard ring plugs (Fig. 2; ¶0018), depositing conductive material into the openings to form guard ring plugs (Fig. 2; ¶0019), removing another portion of first insulating layer 220 to form an opening for through via 330 (Fig. 3; ¶0020), and forming through via 330 in the opening (Fig. 3; ¶0020).
Claim 13 further recites removing first and second portions of the first dielectric layer to define first and second openings, forming first and second guard rings in the respective openings, removing a third portion of the first dielectric layer to define a third opening, and forming a vertical conductive structure in the third opening such that no line extending from the second guard ring intersects the vertical conductive structure without passing through the first guard ring.
Lu expressly teaches these additional limitations in the embodiment illustrated in Figures 7A and 7B. Paragraph 0034 teaches that Figures 7A and 7B provide multiple guard rings comprising guard ring plugs 224A-224D, formed using processes similar to those described with respect to Figures 1-4 by appropriately modifying the photolithographic masks. Accordingly, Lu teaches forming multiple openings in first insulating layer 220, forming first guard ring 224A in a first opening and second guard ring 224C in a second opening, and subsequently forming through via 330 within the inner perimeter of first guard ring 224A.
As illustrated in Figure 7A, first guard ring 224A is positioned entirely between second guard ring 224C and through via 330. Consequently, no line extending from second guard ring 224C intersects through via 330 without first passing through first guard ring 224A, exactly as recited in claim 13.
Accordingly, Lu discloses each and every limitation of claim 13.
Regarding claim 14. Lu discloses The method of claim 13. As discussed above with respect to claim 13, Lu discloses a method comprising removing portions of first insulating layer 220 to define first, second, and third openings, forming first guard ring 224A and second guard ring 224C in the first and second openings, respectively, and forming through via 330 in the third opening (Figs. 2, 3, 7A and 7B; ¶¶0018-0020 and 0034-0035).
Claim 14 further recites:
"wherein the vertical conductive structure is surrounded by the first guard ring on at least four sides."
Lu expressly teaches this limitation. As illustrated in Figure 7A, first guard ring 224A forms a solid closed-loop surrounding through via 330. Paragraph 0035 further teaches that guard ring plug 224A forms a solid shape around through via 330. Accordingly, through via 330 is disposed within the inner perimeter of first guard ring 224A, such that the vertical conductive structure is surrounded by the first guard ring on at least four sides, as claimed.
Therefore, Lu discloses each and every limitation of claim 14.
Regarding claim 16. Lu discloses The method of claim 13. As discussed above with respect to claim 13, Lu discloses a method comprising removing portions of first insulating layer 220 to define first and second openings, forming first guard ring 224A and second guard ring 224C in the respective openings, removing a third portion of first insulating layer 220 to define an opening for through via 330, and forming through via 330 within the first guard ring (Figs. 2, 3, 7A and 7B; ¶¶0018-0020 and 0034-0035).
Claim 16 further recites:
"wherein at least one of the first guard ring or the second guard ring forms a closed-loop."
Lu expressly teaches this limitation. As illustrated in Figure 7A, first guard ring 224A and second guard ring 224C each form a solid closed-loop surrounding through via 330. Paragraph 0035 further teaches that guard ring plugs 224A and 224C form solid shapes around through via 330, in contrast to guard ring plugs 224B and 224D, which form broken shapes. Accordingly, Lu expressly teaches that at least one, and in fact both, of the first and second guard rings form closed loops, as claimed.
Therefore, Lu discloses each and every limitation of claim 16.
Regarding claim 17. Lu discloses a semiconductor arrangement comprising:
a first dielectric layer (first insulating layer 220) formed over substrate 110 (Fig. 4; ¶¶ 0017-0019).
a first guard ring in the first dielectric layer, wherein the first guard ring defines a closed loop (guard ring 446 comprising guard ring plugs 224 formed in first dielectric layer 220, Fig. 4). Lu expressly teaches that the guard ring may have a circular, square, octagonal, rhombus, or other suitable shape (Figs. 5A-5D), and that the guard ring forms an inner region 550 through which the through via 330 is formed, thereby defining a continuous closed-loop guard ring surrounding the inner region.
a vertical conductive structure disposed within an inner perimeter of the closed loop (through via 330 disposed within inner region 550 defined by guard ring 446, as illustrated in Figs. 5A-5D and Fig. 4). Lu further explains that the through vias 330 are formed through the first insulating layer 220 and into substrate 110.
a conductive structure under the first guard ring and the vertical conductive structure. Figure 4 illustrates metallization layers M₁-Mₙ formed over first dielectric layer 220, wherein the metallization layers comprise conductive lines and vias for electrically coupling the electrical circuitry and the through vias. Lu explains that the metallization layers are formed of conductive material, such as copper, and electrically connect the through vias within the semiconductor arrangement (¶¶ 0021-0025). In addition, Lu teaches that the backside of substrate 110 may be thinned to expose the through vias and that contacts and/or redistribution lines may be formed to provide electrical contact to the through vias (¶ 0028). Accordingly, Lu discloses conductive structures associated with the through vias and positioned relative to the first guard ring and the vertical conductive structure as claimed.
Accordingly, Lu expressly discloses each and every limitation of claim 17.
Regarding claim 18. Lu discloses The semiconductor arrangement of claim 17. As discussed above with respect to claim 17, Lu discloses a semiconductor arrangement including a first dielectric layer (first insulating layer 220), a first guard ring 446 formed in the first dielectric layer and defining a closed loop, a vertical conductive structure (through via 330) disposed within the inner perimeter of the closed loop, and a conductive structure underlying the first guard ring and the vertical conductive structure.
Claim 18 further recites:
"wherein the conductive structure is in contact with the vertical conductive structure."
Lu expressly teaches this limitation. As illustrated in Figure 4, conductive line 222 is directly connected to and in physical contact with through via 330, thereby electrically coupling the through via to the metallization structure. Lu further teaches that conductive lines 222 and conductive vias 224 are formed of conductive material, such as copper, and together form the metallization structure for electrically coupling the integrated circuitry with the through vias (¶¶0021-0025). Thus, conductive line 222 constitutes the claimed conductive structure and is expressly disclosed as being in contact with vertical conductive structure 330.
Moreover, Lu teaches that after the backside of substrate 110 is thinned to expose the through vias, contacts and/or redistribution lines may be formed to provide electrical contact to the through vias (¶0028), thereby providing additional support that the conductive structures are in direct electrical and physical contact with the through vias.
Accordingly, Lu expressly discloses each and every limitation of claim 18, including the limitation that the conductive structure is in contact with the vertical conductive structure.
Regarding claim 19. Lu discloses The semiconductor arrangement of claim 17. As discussed above with respect to claim 17, Lu discloses a semiconductor arrangement including a first dielectric layer (first insulating layer 220), a first guard ring 446 formed in the first dielectric layer and defining a closed loop, a vertical conductive structure (through via 330) disposed within the inner perimeter of the closed loop, and a conductive structure underlying the first guard ring and the vertical conductive structure.
Claim 19 further recites:
"wherein the vertical conductive structure has a first height and the first guard ring has a second height less than the first height."
Lu expressly teaches this limitation. As illustrated in Figure 4, vertical conductive structure 330 extends through first dielectric layer 220, substrate 110, and into the overlying metallization structure, whereas first guard ring 446 extends through only a portion of the semiconductor arrangement surrounding the vertical conductive structure. Accordingly, Figure 4 expressly illustrates that the height of vertical conductive structure 330 is greater than the height of first guard ring 446, thereby teaching that the first height of the vertical conductive structure is greater than the second height of the first guard ring as claimed.
Therefore, Lu discloses each and every limitation of claim 19.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 20130154048) in view of Kuo et al. (US 20150179580).
Regarding claim 2. Lu discloses The method of claim 1, portion of first insulating layer 220 to define a first opening, forming first guard ring 224 in the first opening, removing another portion of first insulating layer 220 to define an opening for through via 330, and forming through via 330 in the opening (Figs. 2, 3, and 5A-5D; ¶¶0018-0020).
Claim 2 further recites:
"exposing a conductive layer through the opening."
But Lu does not expressly disclose exposing a conductive layer through the opening.
However, Kuo expressly teaches this limitation. Specifically, Kuo discloses that metal layer 44 is embedded within dielectric layer 42. As illustrated in Figure 6, a photo-etching process forms through-hole 52 in dielectric layer 48, thereby exposing conductive (metal) layer 44 before formation of barrier layer 56. Paragraph 0023 explains that the through-hole 52 is formed in dielectric layer 48 prior to deposition of barrier layer 56, as illustrated in Figure 6.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lu's method to expose the conductive layer through the opening as taught by Kuo before forming the vertical conductive structure. Such a modification would have enabled reliable electrical contact between the subsequently formed vertical conductive structure and the underlying conductive layer, thereby achieving the electrical interconnection expressly contemplated by Lu, which teaches that through via 330 electrically communicates with circuitry on the device side of substrate 110. The modification merely applies Kuo's known via-opening technique to Lu's TSV fabrication process to obtain the predictable result of exposing the conductive layer for subsequent electrical connection.
Regarding claim 3. Lu in view of Kuo discloses The method of claim 2, As discussed above with respect to claim 2, Lu discloses removing portions of first insulating layer 220 to define openings for first guard ring 224 and through via 330, forming the first guard ring in the first opening, and forming the through via in the second opening (Figs. 2, 3, and 5A-5D; ¶¶0018-0020). Lu, as modified by Kuo, further teaches exposing a conductive layer through the opening.
Claim 3 further recites:
"forming the vertical conductive structure in contact with the conductive layer."
Kuo expressly teaches this limitation. As illustrated in Figure 6, through-hole 52 is formed through dielectric layer 48 to expose conductive layer 44 before formation of the vertical conductive structure (¶0023). Subsequently, Figure 7 illustrates formation of barrier layer 56 and seed layer 62 along the sidewalls and bottom of through-hole 52, wherein seed layer 62 is formed directly on the exposed conductive layer 44 (¶0024). Thereafter, as illustrated in Figure 8, conductive material 64 is deposited on seed layer 62 to fill through-hole 52, thereby completing the vertical conductive structure, which is in physical and electrical contact with conductive layer 44 through seed layer 62 (¶0025).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the vertical conductive structure in contact with the exposed conductive layer as taught by Kuo in order to provide a reliable electrical connection between the vertical conductive structure and the underlying conductive layer. Such a modification merely applies Kuo's known through-via interconnection technique to Lu's semiconductor fabrication process and would have predictably resulted in the vertical conductive structure electrically contacting the conductive layer while preserving Lu's guard-ring arrangement.
Claims 4 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 20130154048).
Regarding claim 4. Lu discloses The method of claim 1. As discussed above with respect to claim 1, Lu discloses removing a portion of first insulating layer 220 to define an opening for guard ring plug 224 by photolithographically patterning a photoresist layer and anisotropically etching first insulating layer 220 (Fig. 2; ¶0018), followed by filling the opening with conductive material to form guard ring plug 224 (Fig. 2; ¶0019).
Claim 4 further recites:
"removing a first portion of a second dielectric layer under the first dielectric layer to further define the first closed-loop opening."
But Lu does not expressly describe removing a portion of an underlying dielectric layer to further define the same opening.
However, Lu teaches, in the embodiment illustrated in Figure 8, a dielectric layer 440 formed over first insulating layer 220, such that first insulating layer 220 is disposed beneath dielectric layer 440 (¶0021). Lu further teaches forming guard rings 662 in dielectric layer 440 (¶0032). As illustrated in Figure 8, guard rings 662 are vertically aligned with and connected to guard ring plugs 224 formed in first insulating layer 220, thereby forming a single continuous closed-loop guard ring extending through dielectric layer 440 and first insulating layer 220.
In view of Lu's disclosure of the continuous guard ring extending through both dielectric layers, it would have been obvious to one of ordinary skill in the art that corresponding openings would be formed through both dielectric layer 440 and the underlying first insulating layer 220 to accommodate the continuous guard ring structure. Accordingly, it would have been obvious to remove a portion of the underlying first insulating layer 220 after removing a corresponding portion of the overlying dielectric layer 440, thereby further defining the same opening through the stacked dielectric layers to receive the continuous guard ring. Such a fabrication sequence represents the predictable and routine process required to produce the continuous guard ring structure expressly disclosed by Lu and would have yielded no more than the expected result of forming a vertically continuous guard ring extending through both dielectric layers.
Regarding claim 20. Lu discloses The semiconductor arrangement of claim 17. As discussed above with respect to claim 17, Lu discloses a semiconductor arrangement including a first dielectric layer (first insulating layer 220), a first guard ring (guard ring 446) defining a closed loop, a vertical conductive structure (through via 330) disposed within the inner perimeter of the closed loop, and a conductive structure underlying the first guard ring and the vertical conductive structure (Figs. 4 and 5A-5D; ¶¶0017-0029).
However, the embodiment illustrated in Figures 4 and 5A-5D does not expressly disclose a second guard ring surrounding the vertical conductive structure and spaced apart from the vertical conductive structure by the first guard ring, as recited in claim 20.
Lu, however, expressly teaches such a guard-ring arrangement in another embodiment. Specifically, Figures 7A and 7B disclose a semiconductor arrangement including multiple guard ring plugs 224A-224D surrounding through via 330. Paragraph 0034 explains that the embodiment of Figures 7A and 7B provides multiple guard rings around the through via using processes similar to those described with respect to Figures 1-4, with appropriate modification of the mask pattern. Paragraph 0035 further teaches that guard ring plugs 224A and 224C form solid closed-loop shapes surrounding through via 330, while guard ring plugs 224B and 224D form broken-loop shapes surrounding the through via. Accordingly, guard ring 224A constitutes a first guard ring surrounding through via 330, and guard ring 224C constitutes a second guard ring surrounding the first guard ring, such that the second guard ring is spaced apart from through via 330 by the first guard ring.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor arrangement of the embodiment shown in Figures 4 and 5A-5D by incorporating the multiple guard-ring arrangement taught in Figures 7A and 7B because Lu expressly teaches that the multiple guard-ring embodiment is formed using substantially the same fabrication process as the embodiment of Figures 1-4, with appropriate modification of the mask pattern (¶0034). Thus, Lu itself suggests applying the alternative guard-ring configuration to the previously disclosed semiconductor arrangement. Such a modification merely substitutes one guard-ring configuration disclosed by Lu for another disclosed by the same reference and would have predictably resulted in a semiconductor arrangement including a second guard ring surrounding the vertical conductive structure and spaced apart therefrom by the first guard ring, as claimed.
Claims 9-12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 20130154048) in view of Tsai et al. (US 20150348874).
Regarding claim 9. Lu discloses The method of claim 1, As discussed above with respect to claim 1, Lu discloses a method for forming a semiconductor arrangement comprising removing a first portion of a first dielectric layer 220 to define a first closed-loop opening (Fig. 2; ¶0018), forming a first guard ring 224 in the first closed-loop opening (Fig. 2; ¶0019), removing a second portion of the first dielectric layer within an inner perimeter of the first guard ring to define an opening for through via 330 (Fig. 3; ¶0020), and forming the vertical conductive structure 330 in the opening (Fig. 3; ¶0020).
Claim 9 further recites:
"forming, on a first substrate comprising the first dielectric layer, a first passivation layer; forming, on a second substrate, a second passivation layer, wherein the second passivation layer surrounds a conductive layer; and adhering the first passivation layer to the second passivation layer prior to removing the first portion of the first dielectric layer."
But Lu does not teach forming respective passivation layers on first and second substrates, adhering the passivation layers together, and thereafter removing the first portion of the first dielectric layer. In particular, Lu forms the guard-ring opening before any passivation-layer bonding and therefore does not disclose the claimed temporal sequence.
However, Tsai expressly teaches these additional limitations. As illustrated in Figure 1A, Tsai discloses a first workpiece 100 including first substrate 102, first dielectric layer 104, and first passivation layer 106, and a second workpiece 200 including second substrate 202, dielectric layer 204, conductive feature 208a, and passivation layer 206 (¶¶[0018]-[0025]). Dielectric layer 204 and passivation layer 206 are directly joined to one another and collectively form a continuous passivation structure on the upper surface of second substrate 202. Conductive feature 208a is embedded within dielectric layer 204, such that the passivation structure (204/206) surrounds the conductive feature prior to formation of an opening.
Tsai further teaches bonding the first and second workpieces by adhering first passivation layer 106 to second passivation layer 206 (Fig. 1B; ¶[0025]). Only after the workpieces have been bonded does Tsai remove material from the first workpiece and subsequently form opening 118, which extends through the passivation structure (206/204) to expose embedded conductive feature 208a, as illustrated in Figure 1C (¶¶[0034]-[0038]). Thus, Tsai expressly teaches adhering the first passivation layer to the second passivation layer prior to removing a portion of the first dielectric layer, exactly as recited in claim 9.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lu's method by incorporating Tsai's bonding sequence, in which opposing passivation structures on respective substrates are bonded before subsequent backside dielectric-removal processing. A skilled artisan would have recognized that performing the bonding operation prior to formation of the guard-ring opening would provide mechanical support to the substrate during subsequent etching operations, improve alignment between the bonded substrates, and facilitate reliable formation of electrical interconnections through the bonded semiconductor structure. Applying Tsai's known pre-etch bonding process to Lu's guard-ring fabrication method would merely substitute one well-known fabrication sequence for another to obtain the predictable result of a bonded semiconductor arrangement capable of undergoing subsequent guard-ring and vertical-conductor formation while maintaining structural integrity and alignment.
Regarding claim 10. Lu in view of Tsai discloses The method of claim 9, As discussed above with respect to claim 9, Lu discloses the guard-ring fabrication process, while Tsai teaches forming first and second passivation structures on respective substrates, adhering the first passivation layer 106 to the second passivation layer 206, and thereafter performing backside processing on the bonded semiconductor structure (Figs. 1A-1C; ¶¶[0018]-[0038]).
Claim 10 further recites:
"removing a first portion of the first substrate to expose the conductive layer."
Tsai expressly teaches this limitation. As illustrated in Figure 1B, after first workpiece 100 is bonded to second workpiece 200, the backside of first substrate 102 is thinned by removing a portion of the first substrate to form opening 110, thereby exposing portions of the underlying semiconductor structure for subsequent processing (¶¶[0027]-[0028]). Thereafter, as illustrated in Figure 1C, additional etching forms opening 118, which extends through first dielectric layer 104 to expose conductive feature 208a embedded within the passivation structure of the second workpiece (¶¶[0034]-[0038]).
Thus, Tsai expressly teaches removing a portion of the first substrate after bonding and subsequently exposing the conductive feature through the formed opening.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lu's method by incorporating Tsai's backside substrate-removal process following passivation-layer bonding. A skilled artisan would have recognized that thinning or partially removing the first substrate after bonding facilitates subsequent formation of backside openings while maintaining structural support from the bonded second substrate. Such processing was a well-known technique for manufacturing three-dimensional semiconductor devices and would have predictably enabled formation of Lu's guard-ring and vertical-conductive-structure arrangement after substrate bonding.
Regarding claim 11. Lu in view of Tsai discloses The method of claim 9, As discussed above with respect to claim 9, Lu discloses a method for forming a semiconductor arrangement including removing a first portion of first dielectric layer 220 to define a first closed-loop opening (Fig. 2; ¶0018), forming first guard ring 224 in the first closed-loop opening (Fig. 2; ¶0019), removing another portion of first dielectric layer 220 to define an opening for through via 330 (Fig. 3; ¶0020), and forming through via 330 in the opening (Fig. 3; ¶0020).
Claim 11 further recites:
"forming the first dielectric layer on a substrate; and removing a first portion of the substrate to further define the first opening."
Lu discloses first dielectric layer 220 formed on substrate 110, but does not expressly teach removing a portion of the substrate to further define the first opening.
Tsai, however, expressly teaches this limitation. As illustrated in Figure 1A, Tsai discloses first substrate 102 having first dielectric layer 104 formed thereon. After bonding the workpieces, Tsai forms first opening 110 from the backside of first substrate 102, as illustrated in Figure 1B (¶¶0027-0028). Tsai then performs a subsequent etching process to form second opening 118, wherein second opening 118 extends first opening 110 through first dielectric layer 104 toward the underlying conductive features, as expressly described in paragraph 0035 and illustrated in Figure 1C. Accordingly, Tsai teaches removing a portion of the substrate and continuing the etching process to further define the previously formed opening, as recited in claim 11.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lu's method by incorporating Tsai's sequential opening-formation process, in which an initially formed opening is subsequently extended through the substrate and dielectric layers. A skilled artisan would have recognized that such a process provides improved etch control, alignment accuracy, and reliable access to underlying conductive features while maintaining the structural integrity of the bonded semiconductor assembly. Applying Tsai's known opening-extension technique to Lu's guard-ring fabrication process would have predictably resulted in removing a portion of the substrate to further define the previously formed opening before subsequent formation of the vertical conductive structure.
Regarding claim 12. Lu discloses The method of claim 1, Lu discloses a method for forming a semiconductor arrangement comprising removing a first portion of first dielectric layer 220 to define a first closed-loop opening (Fig. 2; ¶0018), forming first guard ring 224 in the first closed-loop opening (Fig. 2; ¶0019), removing another portion of first dielectric layer 220 to define an opening for through via 330 (Fig. 3; ¶0020), and forming through via 330 in the opening (Fig. 3; ¶0020).
Claim 12 further recites:
"forming the first dielectric layer on a substrate; and removing a first portion of the substrate to further define the first closed-loop opening."
Lu discloses first dielectric layer 220 formed on substrate 110, but does not expressly teach removing a portion of the substrate to further define the previously formed first closed-loop opening.
However, Tsai expressly teaches this limitation. As illustrated in Figure 1A, Tsai discloses first substrate 102 having first dielectric layer 104 formed thereon. After bonding the workpieces, Tsai forms first opening 110 from the backside of first substrate 102, as shown in Figure 1B (¶¶0027-0028). Tsai subsequently performs an additional etching process to form second opening 118, wherein second opening 118 extends first opening 110 through first dielectric layer 104 toward the underlying conductive features, as expressly described in paragraph 0035 and illustrated in Figure 1C. Thus, Tsai teaches removing a portion of the substrate and continuing the etching process to further define the previously formed opening, corresponding to the claimed step of removing a first portion of the substrate to further define the first closed-loop opening.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lu's method by incorporating Tsai's sequential opening-extension process. A skilled artisan would have recognized that extending an initially formed opening through the substrate after bonding provides improved etch control, alignment accuracy, and reliable access to underlying conductive structures while maintaining mechanical support of the bonded assembly. Applying Tsai's known substrate-removal and opening-extension technique to Lu's guard-ring fabrication process would have predictably resulted in removing a portion of the substrate to further define the previously formed guard-ring opening before subsequent semiconductor processing.
Regarding claim 15. Lu discloses The method of claim 13. As discussed above with respect to claim 13, Lu discloses a method comprising removing first and second portions of first dielectric layer 220 to define first and second openings, forming first guard ring 224A and second guard ring 224C in the respective openings, removing a third portion of first dielectric layer 220 to define an opening for through via 330, and forming through via 330 in the opening such that no line extending from second guard ring 224C intersects through via 330 without passing through first guard ring 224A (Figs. 2, 3, 7A and 7B; ¶¶0018-0020 and 0034-0035).
Claim 15 further recites:
"forming the first dielectric layer on a substrate; and removing a first portion of the substrate to further define the first opening."
Lu discloses first dielectric layer 220 formed on substrate 110, but does not expressly teach removing a portion of the substrate to further define the first opening.
However, Tsai expressly teaches this limitation. As illustrated in Figure 1A, Tsai discloses first substrate 102 having first dielectric layer 104 formed thereon. After bonding the first and second workpieces, Tsai forms first opening 110 from the backside of first substrate 102, as illustrated in Figure 1B. Tsai subsequently performs an additional etching process to form second opening 118, wherein second opening 118 extends first opening 110 through first dielectric layer 104 toward the underlying conductive features, as expressly described in paragraph 0035 and illustrated in Figure 1C. Thus, Tsai teaches removing a portion of the substrate and continuing the etching process to further define the previously formed opening, corresponding to the claimed step of removing a first portion of the substrate to further define the first opening.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lu's method by incorporating Tsai's sequential opening-extension process, in which an opening initially formed from the backside of a bonded workpiece is subsequently extended through the substrate and dielectric layers. A skilled artisan would have recognized that such a process provides improved etch control, maintains alignment with underlying conductive structures, and preserves mechanical support during backside processing. Applying Tsai's known substrate-removal and opening-extension technique to Lu's method would have predictably resulted in removing a portion of the substrate to further define the first opening while preserving Lu's multiple guard-ring arrangement.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 10A-3P.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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