DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 10, 12-14, 15-16, 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by An et al. (US 2018/0011369 A1 hereinafter referred to as “An”).
With respect to claim 1, An discloses, in Figs.1-11, a display device, comprising: a display panel (10) that includes a pad electrode (P/PP2) (see Par.[0033]-[0036] wherein FIG. 2 illustrates a pad P of a plurality of pads P included in the pad portion PP2 of the display panel 10 of FIG. 1; the pads P of the pad portion PP2 may be arranged, for example, along the first direction D1 at predetermined intervals. In addition, the pads P may be arranged in a single row or in a plurality of rows; see Par.[0038] wherein the pad P includes a first pad electrode PE1 and a second pad electrode PE2; see Par.[0045] wherein a first end of the first pad electrode PE1 may be connected to a wire L, which is connected to a signal line of the display panel 10, and the first pad electrode PE1 may be an extension portion of the wire L); a data driver (400/410) disposed on the display panel (10), the data driver (410) including a bump electrode (B) that corresponds to the pad electrode (P); and an adhesive layer (20) that includes a nano-conductive particle (CP) in contact with the pad electrode (P) and the bump electrode (B) (see Par.[0030]-[0033] wherein as shown in FIG. 1, the data driver is included in an integrated circuit chip 400; the data driver may be mounted on the flexible PCB 50 as an integrated circuit chip; see Par.[0038] wherein the integrated circuit chip 400 includes a substrate 410 and a bump B protruding downwardly from the substrate 410; an anisotropic conductive layer 20, including conductive particles CP, may be disposed between the pad portion PP2 and the integrated circuit chip 400, and at least one conductive particle CP is disposed between the pad P and the bump B), wherein the pad electrode (PP2) includes: a dielectric pattern (160) that protrudes more than surroundings of the pad electrode (P) (see Par.[0042] wherein an interlayer insulating layer 160 may be disposed between the first pad electrode PE1 and the second pad electrode PE2); a conductive pattern (PE2) that covers the dielectric pattern (160); and a dielectric layer (OL) that covers the conductive pattern (PE2), wherein the nano-conductive particle (CP) penetrates the dielectric layer (OL) to contact the conductive pattern (PE2) (see Par.[0079]-[0081] wherein FIG. 8 is a cross-sectional view illustrating the adhesive material of the anisotropic conductive layer 20 may be cured by using heat, light, etc. When the aciform conductive particle CP is used as a conductive particle, although a relatively low pressure is applied to the anisotropic conductive layer 20, the aciform conductive particles CP may penetrate an oxide layer OL disposed on the surface of the second pad electrode PE2).
With respect to claim 2, An discloses, in Figs.1-11, the display device, wherein a diameter of the nano-conductive particle is in a range of about 50 nanometers to about 100 nanometers (see Par.[0039] wherein a diameter of the conductive particle CP may be, for example, equal to or less than about 5 μm (e.g.; 100 nm is less than 5000nm), about 2 to 4 μm, about 2.8 to 3.4 μm, or about 3.0 to 3.2 μm, but the present invention is not limited thereto).
With respect to claim 3, An discloses, in Figs.1-11, the display device, wherein the pad electrode (P) and the bump electrode (B) are electrically connected to each other through the nano-conductive particle (CP) (see Figs.4, 8).
With respect to claim 4, An discloses, in Figs.1-11, the display device, wherein the adhesive layer (20) further includes an adhesive resin, and wherein the nano-conductive particle (CP) includes a plurality of nano-conductive particles which are uniformly distributed in the adhesive resin (see Par.[0082] wherein the anisotropic conductive layer 20 includes the conductive particles CP suspended in an adhesive layer 22, and the adhesive layer 22 is a resin layer that is not cured).
With respect to claim 5, An discloses, in Figs.1-11, the display device, wherein the adhesive layer (20) further includes an adhesive resin, wherein the nano-conductive particle (CP) is disposed on a bottom surface of the data driver (410), and between the pad electrode (PE2) and the bump electrode (B) (see Fig.4).
With respect to claim 6, An discloses, in Figs.1-11, the display device, wherein the diameter of the nano-conductive particle (CP) is greater than a thickness of the dielectric layer (OL) (see Fig.8).
With respect to claim 7, An discloses, in Figs.1-11, the display device, wherein the thickness of the dielectric layer (OL) is in a range of about 10 nanometers to about 30 nanometers (see Par.[0039] wherein a diameter of the conductive particle CP may be, for example, equal to or less than about 5 μm (e.g.; 100 nm is less than 5000nm), about 2 to 4 μm, about 2.8 to 3.4 μm, or about 3.0 to 3.2 μm, but the present invention is not limited thereto; see Fig.8 wherein thickness of OL is lower than diameter of particle CP).
With respect to claim 8, An discloses, in Figs.1-11, the display device, wherein the pad electrode (PE) has a flat top surface that faces the bump electrode (B) (see Fig.4).
With respect to claim 10, An discloses, in Figs.1-11, the display device, wherein the data driver (410) further includes an integrated circuit disposed on and connected to the bump electrode (B) (see Figs.3-4).
With respect to claim 12, An discloses, in Figs.1-11, a display device, comprising: a base substrate (110); a pad electrode (P) including a plurality of conductive patterns that reside on the base substrate (110) and a dielectric layer (OL) that covers the plurality of conductive patterns (see Par.[0033]-[0036] wherein FIG. 2 illustrates a pad P of a plurality of pads P included in the pad portion PP2 of the display panel 10 of FIG. 1; the pads P of the pad portion PP2 may be arranged, for example, along the first direction D1 at predetermined intervals. In addition, the pads P may be arranged in a single row or in a plurality of rows; see Par.[0038] wherein the pad P of the pad portion PP2 is disposed on a substrate 110 of the display panel 10; the pad P includes a first pad electrode PE1 and a second pad electrode PE2; see Par.[0045] wherein a first end of the first pad electrode PE1 may be connected to a wire L, which is connected to a signal line of the display panel 10, and the first pad electrode PE1 may be an extension portion of the wire L); a data driver (410) including a bump electrode that corresponds to the pad electrode (P) (see Par.[0030]-[0033] wherein as shown in FIG. 1, the data driver is included in an integrated circuit chip 400; the data driver may be mounted on the flexible PCB 50 as an integrated circuit chip; see Par.[0038] wherein the integrated circuit chip 400 includes a substrate 410 and a bump B protruding downwardly from the substrate 410; an anisotropic conductive layer 20, including conductive particles CP, may be disposed between the pad portion PP2 and the integrated circuit chip 400, and at least one conductive particle CP is disposed between the pad P and the bump B); and an adhesive layer (20) disposed between the pad electrode (P) and the bump electrode (B), the adhesive layer (20) including a plurality of nano-conductive particles (CP), wherein the plurality of nano-conductive particles (CP) are in contact with the conductive patterns (PE) and are surrounded by the dielectric layer (OL) (see Par.[0079]-[0081] wherein FIG. 8 is a cross-sectional view illustrating the adhesive material of the anisotropic conductive layer 20 may be cured by using heat, light, etc. When the aciform conductive particle CP is used as a conductive particle, although a relatively low pressure is applied to the anisotropic conductive layer 20, the aciform conductive particles CP may penetrate an oxide layer OL disposed on the surface of the second pad electrode PE2).
With respect to claim 13, An discloses, in Figs.1-11, the display device, wherein the plurality of nano-conductive particles penetrate the dielectric layer to come into contact with the conductive patterns, the plurality of nano-conductive particles are in contact with the bump electrode, and the bump electrode and the conductive patterns are electrically connected to each other through the plurality of nano-conductive particles (see Figs.3-4).
With respect to claim 14, An discloses, in Figs.1-11, the display device, wherein a diameter of each of the plurality of nano-conductive particles is in a range of about 50 nanometers to about 100 nanometers (see Par.[0039] wherein a diameter of the conductive particle CP may be, for example, equal to or less than about 5 μm (e.g.; 100 nm is less than 5000nm), about 2 to 4 μm, about 2.8 to 3.4 μm, or about 3.0 to 3.2 μm, but the present invention is not limited thereto).
With respect to claim 15, An discloses, in Figs.1-11, the display device, wherein the adhesive layer further includes an adhesive resin, wherein the plurality of nano-conductive particles are uniformly distributed in the adhesive resin (see Figs.3-4).
With respect to claim 16, An discloses, in Figs.1-11, the display device, wherein the plurality of nano-conductive particles (CP) are disposed between a bottom surface of the data driver (410), the pad electrode (P), and the bump electrode (B) (see Figs.3-4).
With respect to claim 19, An discloses, in Figs.1-11, the display device, wherein a diameter each of the plurality of nano-conductive particles is greater than a thickness of the dielectric layer (see Par.[0039] wherein a diameter of the conductive particle CP may be, for example, equal to or less than about 5 μm (e.g.; 100 nm is less than 5000nm), about 2 to 4 μm, about 2.8 to 3.4 μm, or about 3.0 to 3.2 μm, but the present invention is not limited thereto; see Fig.8 wherein thickness of OL is lower than diameter of particle CP).
Claims 1, 3-6, 8, 10, 12-13, 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsumura et al. (US 2023/0110093 A1 hereinafter referred to as “Matsumura”).
With respect to claim 1, Matsumura discloses, in Figs.1A-24, a display device, comprising: a display panel that includes a pad electrode (81) (see Par.[0043] wherein the detection apparatus 120 having an illumination device may be provided with a display panel instead of the illumination device 121, as illustrated in FIG. 1B; the display panel may be, for example, an organic electroluminescent (EL) (organic light-emitting diode (OLED)) display panel or an inorganic EL (micro-LED or mini-LED) display panel; alternatively, the display panel may be a liquid crystal display (LCD) panel using liquid crystal elements as display elements or an electrophoretic display (EPD) panel using electrophoretic elements as the display elements; see Par.[0101]-[0110] wherein as illustrated in FIG. 9, the first terminal 81 includes a first metal layer ML1, a second metal layer ML2, a third metal layer ML3, and a first light-transmitting conductive layer CL1); a data driver (110) disposed on the display panel, the data driver (110) including a bump electrode (111) that corresponds to the pad electrode (81) (see Par.[0045]-[0046] wherein the substrate 21 is electrically coupled to a control substrate 101 through a wiring substrate 110; the wiring substrate 110 is, for example, a flexible printed circuit board or a rigid circuit board; the wiring substrate 110 is provided with the detection circuit 48 and connects to control substrate 101 (see Fig.2); the control substrate 101 is provided with the control circuit 102 and the power supply circuit 103; the control circuit 102 is, for example, a field-programmable gate array (FPGA); the control circuit 102 supplies control signals to the sensor unit 10, the scan line drive circuit 15, and the signal line selection circuit 16 to control an operation of the sensor unit 10; the power supply circuit 103 supplies voltage signals including, for example, a power supply potential VDD (e.g.; in a data driver (such as in displays, memory interfaces, or I/O circuits), VDD supplies the positive voltage needed for the internal logic) and a reference potential VCOM (refer to FIG. 4) to the sensor unit 10, the scan line drive circuit 15, and the signal line selection circuit 16); and an adhesive layer (113) that includes a nano-conductive particle (114) in contact with the pad electrode (81) and the bump electrode (111), wherein the pad electrode includes: a dielectric pattern (24-25) that protrudes more than surroundings of the pad electrode (81) (see Par.[0111] wherein as illustrated in FIG. 10, the undercoat film 22 and the insulating films 23, 24, and 25 of array substrate 2 are continuously formed from the detection region AA to the peripheral region GA in which the first terminal 81 is provided; see Par.[0117] wherein As illustrated in FIG. 11, the first metal layer ML1 is formed to have a width in the second direction Dy larger than the width in the second direction Dy of the opening OP; the first contact portions CN1 are provided on the second direction Dy side (detection region AA side) of the opening OP, and pass through the insulating films 24 and 25 that protrude); a conductive pattern (ML, CL) that covers the dielectric pattern (24-25); and a dielectric layer (28) that covers the conductive pattern (CL, ML), wherein the nano-conductive particle (114) penetrates the dielectric layer (28) to contact the conductive pattern (CL, ML) (see Par.[0118] wherein as illustrated in FIG. 12, the wiring substrate terminal 111 of the wiring substrate 110 faces the first terminal 81 with the anisotropic conductive film 112 interposed therebetween; the anisotropic conductive film 112 includes a resin layer 113 and a number of conductive particles 114 dispersed in the resin layer 113, and is provided above the insulating film 28 so as to cover the first terminal 81; the anisotropic conductive film 112 is in direct contact with a side surface of the insulating film 28 forming the opening OP and with the first light-transmitting conductive layer CL1 overlapping the opening OP).
With respect to claim 3, Matsumura discloses, in Figs.1A-24, the display device, wherein the pad electrode (81) and the bump electrode (111) are electrically connected to each other through the nano-conductive particle (114) (see Fig.12).
With respect to claim 4, Matsumura discloses, in Figs.1A-24, the display device, wherein the adhesive layer (112) further includes an adhesive resin (113), and wherein the nano-conductive particle (114) includes a plurality of nano-conductive particles (114) which are uniformly distributed in the adhesive resin (113) (see Par.[0118] wherein as illustrated in FIG. 12, the wiring substrate terminal 111 of the wiring substrate 110 faces the first terminal 81 with the anisotropic conductive film 112 interposed therebetween; the anisotropic conductive film 112 includes a resin layer 113 and a number of conductive particles 114 dispersed in the resin layer 113, and is provided above the insulating film 28 so as to cover the first terminal 81).
With respect to claim 5, Matsumura discloses, in Figs.1A-24, the display device, wherein the adhesive layer (112) further includes an adhesive resin (113), wherein the nano-conductive particle (114) is disposed on a bottom surface of the data driver (110), and between the pad electrode (81) and the bump electrode (111) (see Fig.12).
With respect to claim 6, Matsumura discloses, in Figs.1A-24, the display device, wherein the diameter of the nano-conductive particle (114) is greater than a thickness of the dielectric layer (28) (see Fig.12).
With respect to claim 8, Matsumura discloses, in Figs.1A-24, the display device, wherein the pad electrode (81) has a flat top surface that faces the bump electrode (111) (see Fig.12).
With respect to claim 10, Matsumura discloses, in Figs.1A-24, the display device, wherein the data driver (110) further includes an integrated circuit disposed on and connected to the bump electrode (111) (see Fig.12).
With respect to claim 12, Matsumura discloses, in Figs.1A-24, a display device, comprising: a base substrate (21) (see Par.[0044]-[0047] wherein the substrate 21 is electrically coupled to a control substrate 101 through a wiring substrate 110); a pad electrode (81) including a plurality of conductive patterns (CL1, ML3) that reside on the base substrate (21) and a dielectric layer (28) that covers the plurality of conductive patterns (CL1, ML3) (see Par.[0109]-[0110] wherein the third metal layer ML3, and the first light-transmitting conductive layer CL1 are rectangular in the plan view, and are provided so as to overlap one another; see Par.[0114]-[0115] wherein the insulating film 28 is provided above the insulating film 25 so as to cover the first light-transmitting conductive layer CL1 of the first terminal 81; the insulating film 28 is provided with an opening OP to expose the first light-transmitting conductive layer CL1 in a region overlapping each of the first terminals 81); a data driver (110) including a bump electrode (111) that corresponds to the pad electrode (see Par.[0045]-[0046] wherein the substrate 21 is electrically coupled to a control substrate 101 through a wiring substrate 110; the wiring substrate 110 is, for example, a flexible printed circuit board or a rigid circuit board; the wiring substrate 110 is provided with the detection circuit 48 and connects to control substrate 101 (see Fig.2); the control substrate 101 is provided with the control circuit 102 and the power supply circuit 103; the control circuit 102 is, for example, a field-programmable gate array (FPGA); the control circuit 102 supplies control signals to the sensor unit 10, the scan line drive circuit 15, and the signal line selection circuit 16 to control an operation of the sensor unit 10; the power supply circuit 103 supplies voltage signals including, for example, a power supply potential VDD (e.g.; in a data driver (such as in displays, memory interfaces, or I/O circuits), VDD supplies the positive voltage needed for the internal logic) and a reference potential VCOM (refer to FIG. 4) to the sensor unit 10, the scan line drive circuit 15, and the signal line selection circuit 16); and an adhesive layer (112) disposed between the pad electrode (81) and the bump electrode (111), the adhesive layer (112) including a plurality of nano-conductive particles (114), wherein the plurality of nano-conductive particles (114) are in contact with the conductive patterns (CL1, ML3) and are surrounded by the dielectric layer (28) (see Par.[0118] wherein as illustrated in FIG. 12, the wiring substrate terminal 111 of the wiring substrate 110 faces the first terminal 81 with the anisotropic conductive film 112 interposed therebetween; the anisotropic conductive film 112 includes a resin layer 113 and a number of conductive particles 114 dispersed in the resin layer 113, and is provided above the insulating film 28 so as to cover the first terminal 81; the anisotropic conductive film 112 is in direct contact with a side surface of the insulating film 28 forming the opening OP and with the first light-transmitting conductive layer CL1 overlapping the opening OP).
With respect to claim 13, Matsumura discloses, in Figs.1A-24, the display device, wherein the plurality of nano-conductive particles (114) penetrate the dielectric layer (28) to come into contact with the conductive patterns (CL1, ML3), the plurality of nano-conductive particles (114) are in contact with the bump electrode (111), and the bump electrode (111) and the conductive patterns (CL1, ML3) are electrically connected to each other through the plurality of nano-conductive particles (114) (see Fig.12).
With respect to claim 15, Matsumura discloses, in Figs.1A-24, the display device, wherein the adhesive layer (112) further includes an adhesive resin (113), wherein the plurality of nano-conductive particles (114) are uniformly distributed in the adhesive resin (113) (see Par.[0118] wherein as illustrated in FIG. 12, the wiring substrate terminal 111 of the wiring substrate 110 faces the first terminal 81 with the anisotropic conductive film 112 interposed therebetween; the anisotropic conductive film 112 includes a resin layer 113 and a number of conductive particles 114 dispersed in the resin layer 113, and is provided above the insulating film 28 so as to cover the first terminal 81).
With respect to claim 16, Matsumura discloses, in Figs.1A-24, the display device, wherein the plurality of nano-conductive particles are disposed between a bottom surface of the data driver (110), the pad electrode (81), and the bump electrode (111) (see Fig.12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11, 20 are rejected under 35 U.S.C. 103 as being unpatentable over An in view of Cho et al. (US 2013/0240917 A1 hereinafter referred to “Cho”).
With respect to claim 11, An discloses all the claimed limitations of claim 1. However, An does not explicitly disclose the limitations of claim 11.
Cho discloses, in Figs.1-3B, the display device, wherein the nano-conductive particle includes one of chromium and molybdenum (see Par.[0065] wherein Other examples of conductive particles include aluminum, beryllium, iron, silver, platinum, lead, tin, bronze, brass, copper, bismuth, cobalt, magnesium, molybdenum, palladium, tantalum carbide, boron carbide, and other conductive materials that can be dispersed within a material such as a binding agent).
An and Cho are analogous art because they are all directed to a display device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying An to include Cho because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the particle material in An by including molybdenum particle as taught by Cho in order to utilize the conductive materials that can be dispersed within a material such as a binding agent thereby enhancing mechanical properties of the display device.
With respect to claim 20, An discloses all the claimed limitations of claim 12. However, An does not explicitly disclose the limitations of claim 20.
Cho discloses, in Figs.1-3B, the display device, wherein the nano-conductive particle includes one of chromium and molybdenum (see Par.[0065] wherein Other examples of conductive particles include aluminum, beryllium, iron, silver, platinum, lead, tin, bronze, brass, copper, bismuth, cobalt, magnesium, molybdenum, palladium, tantalum carbide, boron carbide, and other conductive materials that can be dispersed within a material such as a binding agent).
An and Cho are analogous art because they are all directed to a display device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying An to include Cho because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the particle material in An by including molybdenum particle as taught by Cho in order to utilize the conductive materials that can be dispersed within a material such as a binding agent thereby enhancing mechanical properties of the display device.
Allowable Subject Matter
Claims 9 and 17-18 are objected to as being dependent upon a rejected base claims 1 and 12 respectively, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art of record teaches, suggest, or renders obvious, either alone or in combination, a first conductive pattern disposed below the dielectric pattern; a second conductive pattern disposed between the first conductive pattern and the dielectric pattern; a third conductive pattern, wherein the third conductive pattern covers the dielectric pattern and is connected to the second conductive pattern; and a fourth conductive pattern disposed on the third conductive pattern, wherein the dielectric pattern protrudes more than surroundings of the pad electrode, and wherein the third conductive pattern and the fourth conductive pattern which are disposed on the dielectric pattern protrude more than surroundings of the pad electrode.
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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