Prosecution Insights
Last updated: October 22, 2026
Application No. 18/780,802

GUARD RING AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103§112
Filed
Jul 23, 2024
Priority
Apr 23, 2021 — provisional 63/178,905 +1 more
Examiner
SNOW, COLLEEN ERIN
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
521 granted / 658 resolved
+19.2% vs TC avg
Moderate +11% lift
Without
With
+11.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
9 currently pending
Career history
670
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
60.1%
+20.1% vs TC avg
§102
27.7%
-12.3% vs TC avg
§112
11.2%
-28.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 658 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 9 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. In particular, claim 9 contains a limitation whereby “the guard ring is a first distance from a lateral position of a guard ring.” This is inherently unclear, as the claim limitation refers to itself. One of ordinary skill in the art would not be able to decipher the relative position of the guard ring to itself. For purposes of this Office Action, claim 9 will be treated without this limitation. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 5-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al (US Patent Application Publication 2013/0154048). Regarding claim 1, Lu et al disclose an electronic device, comprising: a first dielectric structure 440 over a second dielectric 220 that is over a substrate 110 [see Fig. 6; see also paragraph 0021]; a first conductive structure 330 extending through the first dielectric structure, the second dielectric structure, and the substrate [see paragraph 0029]; a guard ring 662 extending through the first dielectric structure [see paragraph 0032]; and a second conductive structure 222 in the second dielectric structure [see Fig. 6; see also paragraph 0018]. Regarding claim 5, Lu et al disclose the electronic device of claim 1, furthermore wherein at least one of: the first dielectric structure comprises an inter-metal dielectric structure [see paragraph 0021], or the second dielectric structure comprises an inter-layer dielectric structure [see paragraph 0017]. Regarding claim 6, Lu et al disclose the electronic device of claim 1, furthermore wherein the guard ring is vertically displaced from the first conductive structure and the second conductive structure [see Fig. 6]. Regarding claim 7, Lu et al disclose the electronic device of claim 1, furthermore wherein the guard ring comprises multiple layers with different lateral distances from one or more of the first conductive structure or the second conductive structure [see Fig. 6]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al (US Patent Application Publication 2013/0154048) in view of Lai et al (US Patent Application Publication 2022/0238522). Regarding claim 2, Lu et al disclose the electronic device of claim 1. Lu et al disclose a third conductive structure in the second dielectric layer, but do not disclose a third conductive structure on the second conductive structure. One such as Lai et al disclose a first dielectric structure 74 that is over a second dielectric structure 48 that is over a substrate 20; a second conductive structure 70 in the second dielectric structure, and a third conductive structure 86 in the second dielectric structure and on the second conductive structure [see Fig. 19; see also paragraphs 0039-0040]. It would have been obvious to one of ordinary skill in the art at the time of invention to include the third conductive structure of Lai et al in the electronic device of Lu et al because Lai et al teach that providing the additional conductive structure so as to contact the underlying conductive structure at both its top surface and sidewall improves adhesion and reduces contact resistance [see paragraphs 0008 and 0047]. Regarding claims 3 and 4, the prior art of Lu et al and Lai et al disclose the electronic device of claim 2. Furthermore, Lai et al disclose wherein a first side of the second conductive structure is at a same lateral position in the electronic device as a first side of the third conductive structure, and wherein a second side surface of the second conductive structure is at a different lateral position in the electronic device than a first side of the third conductive structure [see Fig. 19, wherein the second and third conductive structures have an offset geometry]. Claims 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over McGahay et al (US Patent Application Publication 2011/0291279) in view of Lin et al (USPN 9,865,523). Regarding claim 8, McGahay et al disclose an electronic device, comprising: a first dielectric structure 114B over a second dielectric 114A that is over a substrate 112 [see Fig. 5C; see also paragraph 0027]; a first conductive structure 122 that extends through the first dielectric structure, the second dielectric structure, and the substrate [see Fig. 5E; see also paragraph 0027]; a guard ring 144, in the first dielectric structure, having multiple layers extending away from a vertical portion of the first conductive structure [see Fig. 5C; see also paragraph 0027]. McGahay et al do not disclose a second conductive structure in the first dielectric structure and the second dielectric structure. One such as Lin et al disclose an electronic device comprising a first dielectric structure 135 over a second dielectric 130 that is over a substrate 105; a first conductive structure 165 that extends through the first dielectric structure, the second dielectric structure, and the substrate; and a second conductive structure 125 in the first dielectric structure and the second dielectric structure [see Fig. 5]. It would have been obvious to one of ordinary skill in the art at the time of invention to form a second conductive structure in the first dielectric structure and the second dielectric structure of McGahay et al because Lin et al disclose that their BEOL architecture beneficially provides electrical interconnection between conductive features located at different levels, in particular laterally adjacent to a TSV structure [see col. 3, line 61 to col. 4, line 38]. Regarding claim 9, the prior art of McGahay et al and Lin et al disclose the electronic device of claim 8. Furthermore, the combination of the teachings of McGahay et al with the teachings of Lin et al would disclose wherein the second conductive structure is a second distance from the lateral position of the guard ring [see Figs. 5E of McGahay et al and 5 of Lin et al]. Regarding the limitations whereby the guard ring is a first distance from a lateral position of the guard ring, and wherein the second distance is greater than the first distance, see the rejection above under 35 U.S.C. §112. Regarding claim 10, the prior art of McGahay et al and Lin et al disclose the electronic device of claim 8. Furthermore to the second conductive structure, Lin et al disclose wherein the second conductive structure extends through an entirety of the first dielectric structure and through a portion of the second dielectric structure [see Fig. 5]. Regarding claims 11 and 12, the prior art of McGahay et al and Lin et al disclose the electronic device of claim 8. Furthermore to the second conductive structure, Lin et al disclose comprising a third conductive structure in the second dielectric structure, wherein the second conductive structure intersects with the third conductive structure in the second dielectric structure [see Fig. 5]. Regarding claim 13, the prior art of McGahay et al and Lin et al disclose the electronic device of claim 8. Furthermore, while neither McGahay et al nor Lin et al specifically disclose wherein at least one of the first dielectric structure comprises an inter-metal dielectric structure, or the second dielectric structure comprises an inter-layer dielectric structure, the first dielectric structure and the second dielectric structure of McGahay et al function in exactly that manner. Regarding claim 14, the prior art of McGahay et al and Lin et al disclose the electronic device of claim 8. Furthermore, McGahay et al disclose wherein the first conductive structure extends through an entirety of the first dielectric structure and the second dielectric structure, and through a portion of the substrate [see Fig. 5D]. Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (USPN 9,865,523) in view of McGahay et al (US Patent Application Publication 2011/0291279). Regarding claim 15, Lin et al disclose a method of forming an electronic device, comprising: forming a first conductive structure through a first dielectric structure 135, a second dielectric structure 130, and a substrate 105, wherein the first dielectric structure is over the second dielectric structure, and wherein the second dielectric structure is over the substrate; and forming a second conductive structure 127 in the second dielectric structure. Lin et al do not disclose forming a guard ring in the first dielectric structure. One such as McGahay et al disclose a method of forming an electronic device, comprising: forming a first conductive structure 122 through a first dielectric structure 114B, a second dielectric structure 114A, and a substrate 112, wherein the first dielectric structure is over the second dielectric structure, and wherein the second dielectric structure is over the substrate; and forming a guard ring 144 in the first dielectric structure. It would have been obvious to one of ordinary skill in the art at the time of invention to include the step of forming the guard ring structure of McGahay et al in the method of Lin et al in order to protect the surrounding dielectric material of the BEOL from deleterious effects associated with formation of a TSV, including migration of moisture and metal into the dielectric material [see McGahay et al, paragraph 0017]. Regarding claims 16-18, the prior art of Lin et al and McGahay et al disclose the method of claim 15. Furthermore, Lin et al disclose forming a third conductive structure in the second dielectric structure and on the second conductive structure, wherein a first side of the second conductive structure is at a same lateral position in the electronic device than a first side of the third conductive structure, and wherein a second side of the second conductive structure is at a different lateral position in the electronic device than a first side of the third conductive structure [see Fig. 5]. Regarding claim 19, the prior art of Lin et al and McGahay et al disclose the method of claim 15. Furthermore, while neither McGahay et al nor Lin et al specifically disclose wherein at least one of the first dielectric structure comprises an inter-metal dielectric structure, or the second dielectric structure comprises an inter-layer dielectric structure, the first dielectric structure and the second dielectric structure of McGahay et al function in exactly that manner. Regarding claim 20, the prior art of Lin et al and McGahay et al disclose the method of claim 15. Furthermore to the guard ring, McGahay et al disclose wherein the guard ring is vertically displaced from the first conductive structure and the second conductive structure [see Fig. 5E]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLLEEN E SNOW whose telephone number is (571)272-8603. The examiner can normally be reached M-W, 8am-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.E.S./Examiner, Art Unit 2899 /VICTOR A MANDALA/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jul 23, 2024
Application Filed
Oct 07, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12740398
INTERCONNECT LEVELS WITH MULTIPLE LINE TYPES
3y 3m to grant Granted Sep 15, 2026
Patent 12727322
DISPLAY APPARATUS
3y 8m to grant Granted Sep 01, 2026
Patent 12721135
INTEGRATED CIRCUIT DEVICE
3y 3m to grant Granted Aug 25, 2026
Patent 12713954
ELECTRONIC APPARATUS
2y 8m to grant Granted Aug 18, 2026
Patent 12707794
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE
3y 1m to grant Granted Aug 11, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
90%
With Interview (+11.1%)
2y 11m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 658 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month