Prosecution Insights
Last updated: August 17, 2026
Application No. 18/780,824

Semiconductor Device and Manufacturing Method of Semiconductor Device

Non-Final OA §102§103
Filed
Jul 23, 2024
Priority
Jan 13, 2021 — provisional 63/136,737 +2 more
Examiner
CRAWFORD EASON, LATANYA N
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
79%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
730 granted / 931 resolved
+18.4% vs TC avg
Minimal +0% lift
Without
With
+0.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
43 currently pending
Career history
971
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
54.3%
+14.3% vs TC avg
§102
31.1%
-8.9% vs TC avg
§112
11.1%
-28.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 931 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s)10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ishitani (US Pub no. 2021/0167278 A1) Regarding claim 10, Ishitani et al discloses a memory device comprising: a first transistor (110)on a semiconductor substrate(sub) [0056]; a spin Hall electrode(20) disposed over the semiconductor substrate(sub) and electrically coupled to a first terminal (Cw)of the first transistor(110)[0069], the spin Hall electrode (21)comprising: a first metal layer(20a)[0126]; a first spacer layer(20b) over the first metal layer(20a)[0126]; a second metal layer(20a) over the first spacer layer(20b) [0126]; a second spacer layer (20b)over the second metal layer(20a) [0126-0127]; and a third metal layer (20a)over the second spacer layer(20b) [0126-0127]; and a magnetic tunnel junction (10)over the spin Hall electrode(21)[0110][0126-0127]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kan (US Pub no. 20180061467 A1) in view of Lee (US Pub no. 2021/0367142 A1- cited in IDS). Regarding claim 1, Kan et al discloses A semiconductor device, comprising: a memory cell comprising: a first driving transistor (820)electrically connected to a first terminal (M4)of a spin Hall electrode(840)[0085-0086] fig . 8; a second driving transistor (822)electrically connected to a second terminal (M4) of the spin Hall electrode(840) [0085-0086] fig. 8; and a magnetic tunnel junction(830) disposed on an opposite side of the spin Hall electrode(840) as the first driving transistor (820)and the second driving transistor(822) fig. 8 [0085-0086]. Kan et al fails to teach wherein the spin hall electrode is a composite spin Hall electrode comprising: a first metal layer; an oxide layer over the first metal layer; and a second metal layer over the oxide layer. However, Lee et al discloses a composite spin Hall electrode comprises: a first metal layer(134); an oxide layer (136)over the first metal layer(134) [0031]; and a second metal layer (132)over the oxide layer(136) [0031]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kan et al with the teachings of Lee et al to provide a magnetic memory device with improved switching and tunnel-magnetoresistance properties. Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kan (US Pub no. 20180061467 A1) in view of Lee (US Pub no. 2021/0367142 A1- cited in IDS) as applied to claim 1 and further in view of Tsai (US Pub no 2020/0365653 A1) as cited in IDS. Regarding claim 2, Kan et al as modified by Lee et al discloses all the claim limitations of claim 1 but fails to teach wherein the memory cell further comprises a buffer layer that is disposed between the composite spin Hall electrode and the first driving transistor. However, Tsai et al discloses a buffer layer (20)that is disposed beneath a spin coupling layer(22)[0019]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Kan et al and Lee et al with the teachings of Tsai et al such that a buffer layer that is disposed between the composite spin Hall electrode and the first driving transistor results to improve the properties of the spin orbit coupling layer. Regarding claim 3, Tsai et al discloses wherein the buffer layer(20) comprises magnesium oxide[0019]. Regarding claim 4, Kan et al as modified by Lee et al discloses all the claim limitations of claim 1 but fails to teach wherein the memory cell further comprises a separation layer that is disposed between the composite spin Hall electrode and the magnetic tunnel junction. However, Tsai et al discloses a separation layer(24) that is disposed between a spin orbit coupling layer (22)and the magnetic tunnel junction(26-30)[0021] fig. 5. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify the teachings of Kan et al & Lee et al with the teachings of Tsai et al such that a separation layer that is disposed between the composite spin Hall electrode and the magnetic tunnel junction results maintain the state of the device. Regarding claim 5, Tsai et al discloses wherein the separation layer (24) comprises a dielectric material[0021]. Claim(s) 6 & 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kan (US Pub no. 20180061467 A1) in view of Lee (US Pub no. 2021/0367142 A1) as applied to claim 1 and further in view of Rahman US Pub no. 2020/0227104 A1). Regarding claim 6, Kan et al as modified by Lee et al discloses all the claim limitations of claim 1 but fails to teach wherein the first metal layer comprises a metallic material that is in a metastable state. However, Rahman et al teaches a memory device including SOT material comprising beta /alpha phase tungsten(meta stable) [0042]. Since beta /alpha phase tungsten is one of finite solutions to achieve a stable low resistive SOT material to assist switching in a magnetic junction device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to try in Kan & Lee et al such that the first metal layer comprises a metallic material that is in a metastable state results since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense (KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007)) Regarding claim 7, Lee et al discloses wherein the second metal layer(132) comprises a metallic material that is in a stable state[0031]. Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishitani (US Pub no. 2021/0167278 A1) in view of Gosavi (US Pub no. 2020/0006637 A1). Regarding claim 11, Ishitani et al discloses all the claim limitations of claim 10 but fails to teach further comprising a bit line over and electrically coupled to the magnetic tunnel junction by a conductive via. However, Gosavi et al discloses a bit line (450)over and electrically coupled to the magnetic tunnel junction (452) by a conductive via [0048] fig. 4. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ishitani et al with the teachings of Gosavi et al to provide the capability to read a bit of the MRAM. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishitani (US Pub no. 2021/0167278 A1) in view of Rahman US Pub no. 2020/0227104 A1) Regarding claim 12, Ishitani et al discloses all the claim limitations of claim 10 but fails to teach wherein the first metal layer, the second metal layer, and the third metal layer each comprise a mixture of α-ß-tungsten. However, Rahman et al discloses a memory device including SOT material comprising beta /alpha phase tungsten [0042]. Since beta /alpha phase tungsten is one of finite solutions to achieve a stable low resistive SOT material to assist switching in a magnetic junction device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to try in Ishitani et al such that the first metal layer, the second metal layer, and the third metal layer each comprise a mixture of α-ß-tungsten results since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense (KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007)) Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kan (US Pub no. 20180061467 A1) in view of Shiokawa (US Pub no. 20190057732 A1) Regarding claim 10, Kan et al discloses A memory device comprising: a first transistor (822) on a semiconductor substrate(812); a spin Hall electrode (840)disposed over the semiconductor substrate (812)and electrically coupled to a first terminal (M4) of the first transistor(822) and a magnetic tunnel junction(830) over the spin Hall electrode(840)[0083][0085-0086]. Kan et al fails to teach the spin Hall electrode comprising: a first metal layer; a first spacer layer over the first metal layer; a second metal layer over the first spacer layer; a second spacer layer over the second metal layer; and a third metal layer over the second spacer layer. Shiokawa et al discloses the spin Hall electrode(2) comprising: a first metal layer(3 ); a first spacer layer(4) over the first metal layer(3); a second metal layer(3) over the first spacer layer(4); a second spacer layer (4)over the second metal layer(3); and a third metal layer(3) over the second spacer layer(4)[0039]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kan et al with the teachings of Shiokawa et al to provide a pure spin current caused in a direction orthogonal to a direction of the current on the basis of spin orbit interaction. Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kan (US Pub no. 20180061467 A1) in view of Shiokawa (US Pub no. 20190057732 A1) as applied to claim 10 and further in view of Gosavi (US Pub no. 2020/0006637 A1). Regarding claim 11 Kan et al as modified by Shiokawa et al discloses all the claim limitations of claim 10 but fails to teach further comprising a bit line over and electrically coupled to the magnetic tunnel junction by a conductive via. However, Gosavi et al discloses a bit line (450)over and electrically coupled to the magnetic tunnel junction (452) by a conductive via [0048] fig. 4. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kan et al & Shiokawa et al with the teachings of Gosavi et al to provide the capability to read a bit of the MRAM. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kan (US Pub no. 20180061467 A1) in view of Shiokawa (US Pub no. 20190057732 A1) as applied to claim 10 and further in view of Rahman US Pub no. 2020/0227104 A1) Regarding claim 12, Kan et al as modified by Shiokawa et al discloses all the claim limitations of claim 10 but fails to teach wherein the first metal layer, the second metal layer, and the third metal layer each comprise a mixture of α-ß-tungsten. However, Rahman et al discloses a memory device including SOT material comprising beta /alpha phase tungsten [0042]. Since beta /alpha phase tungsten is one of finite solutions to achieve a stable low resistive SOT material to assist switching in a magnetic junction device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to try in Kan et al & Shiokawa et al such that the first metal layer, the second metal layer, and the third metal layer each comprise a mixture of α-ß-tungsten results since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense (KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007)) Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kan (US Pub no. 20180061467 A1) in view of Shiokawa (US Pub no. 20190057732 A1) as applied to claim 10 and further in view of Smith (US Pub no 2020/0105998 A1) as cited in IDS. Regarding claim 15, Kan et al as modified by Shiokawa et al discloses all the claim limitations of claim 10 but fails to teach further comprising an insulator layer that is disposed between the first metal layer and the semiconductor substrate. However, Smith et al discloses an insulator layer(102) that is disposed between the electrode(101) and the semiconductor substrate(122)[0057][0097]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify the teachings of Kan et al & Shiokawa et al with the teachings of Smith et al to provide electrical isolation. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kan (US Pub no. 20180061467 A1) in view of Shiokawa (US Pub no. 20190057732 A1) in view of Khvalkovskiy (US Pub no 2014/0056061 A1) Regarding claim 16, Kan et al discloses A method, comprising: forming a first driving transistor (820)and a second driving transistor(822) on a substrate(812)[0083][0085-0086] fig . 8; and forming a spin Hall electrode (840)over and electrically coupled to the first driving transistor (820)and the second driving transistor(822). Kan et al fails to teach forming the composite spin Hall electrode comprises: depositing a first metal layer; depositing an amorphous layer on the first metal layer; and depositing a second metal layer on the amorphous layer. However, Shiokawa et al discloses a composite spin Hall electrode(2) comprises: depositing a first metal layer(3); depositing an interfacial spin generation layer (4)on the first metal layer(3); and depositing a second metal layer(3) on the interfacial spin generation layer (4)[0044] but fails to teach the interfacial spin generation layer is amorphous. However, Khvalkovskiy et al discloses hall effect material including high resistive amorphous beta tantalum[0038]. It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify Kan et al & Shiokawa et al to provide a strong spin orbit effect. Allowable Subject Matter Claims 8, 9 , 13,14, 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The limitations of claim 8 including: wherein the first metal layer comprises ß-tungsten, and the second metal layer comprises α-tungsten was not found in prior art. Claim 9 is objected to since the claim depends from claim 8. The limitations of claim 13 including: wherein the first spacer layer and the second spacer layer comprise an amorphous material was not found in prior art. The limitations of claim 14 including: wherein the first spacer layer and the second spacer layer comprise magnesium oxide was not found in prior art. The limitations of claim 17 including: wherein the first metal layer and the second metal layer comprise a mixture of α-ß-tungsten was not found in prior art. The limitations of claim 18 including: wherein the amorphous layer comprises an oxide was not found in prior art. The limitations of claim 19 including: wherein after depositing the amorphous layer on the first metal layer, an arithmetical mean deviation of the surface profile (Ra) of the amorphous layer is less than 0.2 mm was not found in prior art. The limitations of claim 20 including: 20. The method of claim 16, further comprising: annealing the first metal layer, the amorphous layer, and the second metal layer, wherein during the annealing, the first metal layer, the amorphous layer, and the second metal layer are exposed to a perpendicular magnetic field was not found in prior art. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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Prosecution Timeline

Jul 23, 2024
Application Filed
Jul 22, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
79%
With Interview (+0.5%)
2y 8m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 931 resolved cases by this examiner. Grant probability derived from career allowance rate.

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