DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
In paragraph [0027], reference numeral “218” is used to identify two different elements, namely, the “metal capping layer” and the “via hole.”
Appropriate correction is required.
Claim Objections
Claims 1-17, 19 and 20 are objected to because of the following informalities:
In claim 1, line 6, add --of-- between “over top surfaces” and “the dielectric layer.”
In claim 11, line 7, add --first-- before “ESL.”
In claim 15, line 4, add --first-- before “ESL.”
In claim 19, line 1, substitute “claim 17” with --claim 18-- (changing dependency).
In claim 20, line 1, substitute “claim 17” with --claim 18-- (changing dependency).
Claims 2-10, 12-14, 16 and 17 variously depend from claim 1 or 11, so they are objected for the same reason.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites “a selective metal capping layer disposed between the first graphene layer and the selective ESL and between the second graphene layer and the selective ESL.” However, claim 1 recites that the selective ESL is not formed over the top surfaces of the first and the second graphene layers and that sidewalls of the selective ESL directly contact sidewalls of the first and the second graphene layers. Accordingly, claim 6 appears to be inconsistent with claim 1. Specifically, claim 6 requires the selective metal capping layer to be disposed between the graphene layers and the selective ESL, whereas claim 1 expressly excludes the selective ESL from being disposed over the top surfaces of the first and second graphene layers and further requires the sidewalls of the selective ESL to directly contact the sidewalls of the graphene layers, leaving no intervening metal capping layer between those respective sidewalls.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 4 and 7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16-19 of U.S. Patent No. 12,113,021 (hereinafter “Pat-021”). Although the claims at issue are not identical, they are not patentably distinct from each other because Pat-021 discloses all the claimed limitations. See rejections below.
Regarding Claim 1, Pat-021 discloses a semiconductor structure, comprising: a first conductive feature disposed in a dielectric layer (see claim 16); a second conductive feature disposed in the dielectric layer and adjacent to the first conductive feature (see claim 16); first and second graphene layers disposed over top surfaces of the first and the second conductive features, respectively (see claim 16); a selective etch stop layer (ESL) disposed over top surfaces of the dielectric layer (see claim 16) but not over top surfaces of the first and the second graphene layers (the via penetrates through the continuous ESL but not the selective ESL to land on the graphene layer; see claim 18; which means the selective ESL is not formed over the graphene layer), wherein sidewalls of the selective ESL directly contact sidewalls of the first and the second graphene layers (see claim 16); and a via electrically coupled to the first conductive feature by directly contacting the first graphene layer (see claim 16).
Regarding Claim 4, Pat-021 discloses wherein a portion of the via lands on the selective ESL (the via directly contacts a side surface of the selective ESL; see claim 19).
Regarding Claim 7, Pat-021 discloses further comprising a continuous ESL disposed over the selective ESL and over the first and the second graphene layers (a continuous ESL disposed over the selective ESL and over the selective metal capping layer; see claim 17; and the selective metal capping layer is disposed over the graphene layer; see claim 16), wherein the continuous ESL and the selective ESL include different materials (see claim 17).
Allowable Subject Matter
Claim 18 is allowed, and claims 1-17, 19 and 20 will be allowed after overcoming the objections, the 112(b) rejection and nonstatutory double patenting rejections set forth above.
The closest prior art, US Pub. 2014/0284802, discloses a semiconductor structure, comprising: a first conductive feature 17 (left one) disposed in a dielectric layer (11, 12, 13); a second conductive feature 17 (right one) disposed in the dielectric layer (11, 12, 13) and adjacent to the first conductive feature 17 (left one) (fig. 10); first and second graphene layers 19 disposed over top surfaces of the first and the second conductive features 17, respectively (fig. 10); an etch stop layer (ESL) 21 disposed over top surfaces of the dielectric layer (11, 12, 13), wherein sidewalls of the selective ESL 21 directly contact sidewalls of the first and the second graphene layers 19 (fig. 10); and a via 29 electrically coupled to the first conductive feature 17 by directly contacting the first graphene layer 19 (fig. 10).
However, the prior art differs from the present invention because the prior art fails to disclose a selective etch stop layer not over top surfaces of the first and the second graphene layers; selectively forming a first etch-stop layer (ESL) over the top surface of the first ILD layer without forming the first ESL over a top surface of the graphene layer; and depositing an amorphous carbon layer over the first ESL and over the top surfaces of the first and the second conductive features, and performing a carbon dissolution process.
The following is an examiner’s statement of reasons for allowance:
Claim 1 recites a selective etch stop layer (ESL) disposed over top surfaces of the dielectric layer but not over top surfaces of the first and the second graphene layers.
Claim 11 recites selectively forming a first etch-stop layer (ESL) over the top surface of the first ILD layer without forming the first ESL over a top surface of the graphene layer.
Claim 18 recites selectively forming a first etch-stop layer (ESL) over a top surface of the first ILD layer without forming the first ESL over top surfaces of the first and the second conductive features; depositing an amorphous carbon layer over the first ESL and over the top surfaces of the first and the second conductive features; performing a carbon dissolution process to cause carbon atoms of the amorphous carbon layer to migrate towards the first and the second conductive features; and removing the amorphous carbon layer.
These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 2-10, 12-17, 19 and 20 variously depend from claim 1, 11 or 18, so they will be allowed for the same reason.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 September 25, 2026
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