Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 8-9 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 8, the phrase "the dielectric feature includes a same material as that of the high-k gate dielectric layers" is indefinite because the pronoun "that" lacks a clear antecedent basis. It is unclear what "that" refers to (e.g., the material, composition, or another characteristic of the high-k gate dielectric layers). Therefore, the scope of the claim cannot be determined with reasonable certainty
Regarding claim 9, the phrase "the dielectric feature includes a same material as that of the interfacial layers" is indefinite because the pronoun "that" lacks a clear antecedent basis. It is unclear what "that" refers to (e.g., the material, composition, or another characteristic of the interfacial layers). Therefore, the scope of the claim cannot be determined with reasonable certainty.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Examiner conducted a comprehensive analysis of obviousness analysis including the Graham v. Deere analysis for each claim by (A) determining the scope and content of a reference claim relative to the claim in the application at issue; (B) determining the differences between the scope and content of the reference claim as determined in (A) and the claim in the application at issue; (C) determining the level of ordinary skill in the pertinent art; and (D) evaluation any objective indicia of nonobviousness.
The examiner has concluded that there is issue of double patenting rejection in the current application. This is because the claims in this application are deemed to be patentably does not distinct from any claims in a potential double patenting reference. Moreover, the examined application's claim is either anticipated or obvious over the reference claim(s).
Claims 1-5, 7-8 and 10-11 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12107131 (hereinafter “Pat-31”) in view of Kang et al. (US 20200083219).
Regarding claim 1. Claim 1 of Pat-31 discloses the limitations of instant claim 1 as follows:
A semiconductor device, comprising:
a first interconnect structure;
multiple channel layers stacked over the first interconnect structure, wherein a bottommost one of the multiple channel layers is thinner than the rest of the multiple channel layers;
a gate stack wrapping around each of the multiple channel layers except the bottommost one of the multiple channel layers; and
a dielectric feature under the bottommost one of the multiple channel layers.
However, Pat-31 does not disclose wherein the dielectric feature is thinner than portions of the gate stack vertically between channel layers of the multiple channel layers.
Kang teaches this limitation. Specifically, Fig. 3A discloses dielectric feature 154 (154A) disposed beneath the bottommost channel layer that is thinner than portions of the gate stack 160S disposed vertically between adjacent channel layers. Paragraph [0027] teaches that the dielectric feature has a first height H11 and the gate stack portions have a second height H12, wherein the second height H12 is greater than the first height H11, and paragraph [0037] identifies dielectric feature 154 (154A).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Pat-31 to provide the dielectric feature with a thickness less than the portions of the gate stack vertically between adjacent channel layers, as taught by Kang, in order to achieve the dimensional relationship between the dielectric feature and the gate stack disclosed by Kang, thereby providing a suitable structural configuration for fabrication of the stacked channel semiconductor device.
Regarding claim 2, the claim 1 of Pat-31 in view of Kang discloses the semiconductor device of claim 1. Claim 10 of Pat-31 further discloses inner spacers disposed on sidewalls of the gate stack and vertically between the multiple channel layers. Because the dielectric feature is disposed beneath the bottommost channel layer, as taught by claim 1 of Pat-31 in view of Kang, it would have been obvious to one of ordinary skill in the art to provide corresponding inner spacers on the sidewalls of the dielectric feature in order to electrically isolate the dielectric feature from adjacent conductive structures and to maintain a consistent spacer structure within the stacked channel device.
Regarding claim 3, the claim 1 and claim 10 of Pat-31 in view of Kang teach the semiconductor device of claim 2. But Pat-31 does not expressly disclose wherein the first inner spacers are smaller than the second inner spacers.
However, because Kang teaches that the dielectric feature has a smaller vertical dimension than the gate stack portions between adjacent channel layers (H11 < H12).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dimension the corresponding inner spacers according to the available space adjacent to their respective structures, resulting in the first inner spacers being smaller than the second inner spacers, thereby providing suitable electrical isolation while accommodating the differing structural dimensions of the gate stack and the dielectric feature.
Regarding claim 4, the claim 1 of Pat-31 in view of Kang discloses the semiconductor device of instant claim 1. Specifically, claim 1 of Pat-31 further discloses a source/drain feature adjoining the multiple channel layers, a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature, and the dielectric feature directly contacting the first conductive via.
Regarding claim 5, the claim 1 of Pat-31 in view of Kang discloses the semiconductor device of claim 4, as discussed above. Specifically, claim 1 of Pat-31 recites "a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature" and "a dielectric feature under the bottommost one of the multiple channel layers and directly contacting the first conductive via." Accordingly, the dielectric feature is necessarily disposed vertically between the first conductive via and the bottommost one of the multiple channel layers.
Regarding claim 7, the claim 1 of Pat-31, in view of Kang, teaches the semiconductor device of claim 1. Claim 4 of Pat-31 further teaches that the gate stack includes high-k gate dielectric layers wrapping around each of the channel layers. Kang further teaches that a gate electrode 160 wraps around each of the high-k gate dielectric layers 152, as shown in Fig. 3A. In addition, Kang teaches that the gate dielectric layer 152 may comprise a stack including an interfacial layer and a high-k dielectric layer, wherein the interfacial layer may comprise a silicon oxide layer, a silicon oxynitride layer, or a combination thereof, and the high-k dielectric layer may comprise a material having a dielectric constant greater than that of silicon oxide, such as hafnium oxide.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate stack of Pat-31 to include an interfacial layer between the channel layers and the high-k gate dielectric layers and a gate electrode wrapping around the high-k gate dielectric layers, as taught by Kang, in order to provide the gate stack configuration conventionally used in stacked channel semiconductor devices, thereby facilitating fabrication of the semiconductor device.
Regarding claim 8, claim 1 and claim 4 of Pat-31 teaches the semiconductor device of claim 7. Specifically, claim 4 of Pat-31 recites "high-k gate dielectric layers wrapping around each of the multiple channel layers, and the dielectric feature includes a same material as that of the high-k gate dielectric layers," thereby teaching that the dielectric feature includes the same material as that of the high-k gate dielectric layers, as recited in claim 8.
Regarding claim 10, claim 1 of Pat-31 teach the semiconductor device of claim 1. Claim 6 of Pat-31 recites "a semiconductor fin structure directly below the multiple channel layers and the source/drain feature, wherein the first conductive via is embedded in the semiconductor fin structure," thereby teaching a semiconductor fin structure directly below the multiple channel layers, a source/drain feature adjacent and interfacing the multiple channel layers, and a first conductive via connecting the first interconnect structure to the source/drain feature, wherein the first conductive via is embedded in the semiconductor fin structure. Claim 7 of Pat-31 further recites "the dielectric feature separates the semiconductor fin structure from the bottommost one of the multiple channel layers," thereby teaching the dielectric feature separates the semiconductor fin structure from the bottommost one of the channel layers, as recited in claim 10.
Regarding claim 11, claim 1 of Pat-31 teach the semiconductor device of claim 1. Claim 8 of Pat-31 recites "a dielectric fin structure directly below the multiple channel layers and the source/drain feature, wherein the first conductive via is embedded in the dielectric fin structure," thereby teaching a dielectric fin structure directly below the multiple channel layers, a source/drain feature adjacent and interfacing the multiple channel layers, and a first conductive via connecting the first interconnect structure to the source/drain feature, wherein the first conductive via is embedded in the dielectric fin structure. Claim 9 of Pat-31 further recites "the dielectric feature separates the dielectric fin structure from the bottommost one of the multiple channel layers," thereby teaching the dielectric feature separates the dielectric fin structure from the bottommost one of the channel layers, as recited in claim 11.
Claims 12 and 14-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12107131 (hereinafter “Pat-31”) in view of Shin et al. (US 20210257499).
Regarding claim 12, claims 11 and 12 of Pat-31 disclose the semiconductor device of claim 12, including a first interconnect structure, multiple channel layers stacked over the first interconnect structure, a gate stack wrapping around each of the multiple channel layers except a bottommost one of the multiple channel layers, a source/drain feature adjoining (i.e., adjacent and interfacing) the multiple channel layers, a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature, and a dielectric feature under the bottommost one of the multiple channel layers.
However, Pat-31 does not disclose the gate stack including an interfacial layer over the multiple channel layers, a high-k dielectric layer over the interfacial layer, and a gate electrode over the high-k dielectric layer, wherein the dielectric feature is at least partially surrounded by the interfacial layer.
Shin teaches a gate stack 330 including an interfacial layer 290, a high-k dielectric layer 300, and a gate electrode 320, wherein the interfacial layer 290 is disposed between the channel layers 124 and the high-k dielectric layer 300, and the gate electrode 320 is disposed over the high-k dielectric layer 300. As shown in Fig. 2, the interfacial layer 290 extends beneath and along opposing sidewall portions of the lowermost high-k dielectric layer 300 beneath the bottommost channel layer, such that the lowermost dielectric structure beneath the bottommost channel layer is at least partially surrounded by the interfacial layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Pat-31 to employ the gate stack configuration taught by Shin, including an interfacial layer disposed between the multiple channel layers and the high-k dielectric layer and extending at least partially around the dielectric structure beneath the bottommost channel layer, in order to provide the gate stack configuration taught by Shin for a stacked channel semiconductor device, thereby facilitating fabrication of the semiconductor device.
Regarding claim 14, claims 11-12 of Pat-31 in view of Shin disclose the semiconductor device of claim 12, as discussed above. The claim 13 of Pat-31 recites "the dielectric feature directly contacts the first conductive via," thereby teaching the dielectric feature directly contacts the first conductive via, as recited in claim 14.
Regarding claim 15, claims 11-12 of Pat-31 in view of Shin disclose the semiconductor device of claim 12, as discussed above. Specifically, Pat-31 teaches the dielectric feature under the bottommost one of the multiple channel layers, while Shin teaches a gate stack including a high-k dielectric layer 300 disposed over interfacial layer 290. Shin further teaches that the high-k dielectric layer may comprise a material having a dielectric constant greater than that of silicon oxide, such as hafnium oxide.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Pat-31 by forming the dielectric feature beneath the bottommost channel layer from the high-k dielectric material taught by Shin, in order to employ the high-k dielectric material used in Shin's gate stack configuration for the dielectric feature, thereby providing a suitable dielectric structure for the stacked channel semiconductor device.
Allowable Subject Matter
Claims 1-16 would be allowable if overcome the nonstatutory double patenting rejection.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1. The prior art of record, including Agrawal et al. (US 2021/0202319) and Kang et al. (US 2020/0083219), fails to teach or suggest the claimed combination of features.
Specifically, Agrawal et al. discloses a semiconductor device including a first interconnect structure 120 (Fig. 1; ¶0029), multiple channel layers 141 stacked over the first interconnect structure (Fig. 1; ¶¶0032-0033), and a gate stack surrounding the multiple channel layers (Figs. 1-2; ¶¶0032-0035).
Kang et al. discloses a stacked channel semiconductor device in which the bottommost channel layer N31 is thinner than the remaining channel layers N2 and N3 (Figs. 5A-5B; ¶0053).
However, the prior art of record does not teach or suggest a semiconductor device including a gate stack wrapping around each of the multiple channel layers except the bottommost one of the multiple channel layers, together with a dielectric feature disposed under the bottommost one of the multiple channel layers, wherein the dielectric feature is thinner than portions of the gate stack vertically between adjacent channel layers.
The Examiner considers the claimed arrangement of the gate stack and the dielectric feature beneath the bottommost channel layer, including the relative thickness relationship between the dielectric feature and the portions of the gate stack vertically between adjacent channel layers, to distinguish the claimed invention over the prior art of record.”.
Regarding claim 12. The prior art of record, including Ganguly et al. (US 2021/0408246) and Shin et al. (US 2021/0257499), fails to teach or suggest the claimed combination of features. Specifically, Ganguly et al. discloses a semiconductor device including a first interconnect structure 184 (Fig. 1G; ¶0035), multiple channel layers 109 stacked over the first interconnect structure (Fig. 1G; ¶0022), source/drain features 130 adjacent and interfacing the multiple channel layers (Fig. 1G; ¶¶0022-0025), and a first conductive via connecting the first interconnect structure to the bottom of the source/drain feature (Fig. 1G; ¶0035).
Shin et al. discloses a gate stack 330 including an interfacial layer 290, a high-k dielectric layer 300, and a gate electrode 320, wherein the interfacial layer 290 is disposed between the channel layers 124 and the high-k dielectric layer 300, and the gate electrode 320 is disposed over the high-k dielectric layer 300 (Fig. 2; ¶¶0035-0037). Shin et al. further discloses that the interfacial layer 290 extends beneath and along opposing sidewall portions of the lowermost high-k dielectric layer 300 beneath the bottommost channel layer (Fig. 2; ¶0037).
However, the prior art of record does not teach or suggest a semiconductor device including (i) a gate stack wrapping around each of the multiple channel layers except the bottommost one of the multiple channel layers, and (ii) a dielectric feature disposed under the bottommost one of the multiple channel layers, wherein the dielectric feature is at least partially surrounded by the interfacial layer.
The Examiner considers this claimed arrangement, in which the dielectric feature beneath the bottommost channel layer is at least partially surrounded by the interfacial layer while the gate stack wraps around each of the remaining channel layers, to distinguish the claimed invention over the prior art of record.
Claims 17-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 17. The prior art of record, including Shin et al. (US 2021/0257499), fails to teach or suggest the claimed combination of process steps. Specifically, Shin et al. discloses a method including providing a structure having a substrate 100, a semiconductor layer 105 over the substrate, an isolation feature 130 adjacent sidewalls of the semiconductor layer, and multiple channel layers 124 over the semiconductor layer, wherein the channel layers are surrounded by interfacial layers 290 (Fig. 2; ¶¶0019, 0024, and 0027). Shin et al. further discloses forming a first high-k dielectric layer 300 wrapping around each of the channel layers and over the semiconductor layer (Fig. 2; ¶0029).
However, the prior art of record does not teach or suggest a process in which the first high-k dielectric layer partially fills a first space between the channel layers and partially fills a second space between the semiconductor layer and the bottommost channel layer, followed by forming a low-k dielectric layer such that the first high-k dielectric layer and the low-k dielectric layer collectively completely fill the second space while only partially filling the first space, selectively etching the low-k dielectric layer to remove the low-k dielectric layer from the first space while retaining a portion of the low-k dielectric layer in the second space, and thereafter forming a second high-k dielectric layer over the first high-k dielectric layer and the retained portion of the low-k dielectric layer before forming a gate electrode thereover.
The Examiner considers this particular fabrication sequence, including the selective retention of the low-k dielectric layer in the second space prior to formation of the second high-k dielectric layer, to distinguish the claimed invention over the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 10A-3P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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