DETAILED ACTION
This office action is in response to the preliminary amendment filed on 10/16/2024.
Acknowledgement
The present office action is made with all the suggested amendments being fully considered. Accordingly, pending in this office action are claims 21-40. Claims 1-20 have been canceled.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 7/23/2024 and 8/21/2024. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-22, 24, 26 are rejected under 35 U.S.C. 103 as being unpatentable over Nakazawa (US 2004/0026746) in view of Hong (CN 104425520)
With respect to Claim 21, Nakazawa discloses (Fig. 1) most aspects of the current invention including an integrated chip, comprising:
a polysilicon isolation structure (9/11) extending into a top surface of substrate (1)
an insulator liner (7) lateral separating a sidewall of the polysilicon isolation structure from the substrate
However, Nakazawa does not show wherein the substrate comprises a semiconductor facet underlying the polysilicon isolation structure and having a (111) planar surface, and wherein the (111) planar surface of the semiconductor facet extends upward into a bottom of the polysilicon isolation structure from a bottom surface of the insulator liner.
On the other hand, and in the same field of endeavor, Hong teaches (Fig 1-7) an integrated chip, comprising a polysilicon isolation structure (125), and a semiconductor facet (opening 122; see Fig 5) underlying the polysilicon isolation structure and having a (111) planar surface, and wherein the (111) planar surface of the semiconductor facet extends upward into a bottom of the polysilicon isolation structure from a bottom surface of the insulator liner. Hong teaches the semiconductor facet is formed at a depth deeper than the depth of the groove, to make the bottom of said source/drain leakage current of semiconductor substrate 100 through required path becomes longer, thereby reducing the adjacent leakage current between two MOS transistors.
Therefore, it would have been obvious at the time the invention to one having ordinary skill in the art, or before the effective filing date of the invention to have wherein the substrate comprises a semiconductor facet underlying the polysilicon isolation structure and having a (111) planar surface, and wherein the (111) planar surface of the semiconductor facet extends upward into a bottom of the polysilicon isolation structure from a bottom surface of the insulator liner as taught by Hong, in the device of Nakazawa, because the semiconductor facet is formed at a depth deeper than the depth of the groove, to make the bottom of said source/drain leakage current of semiconductor substrate 100 through required path becomes longer, thereby reducing the adjacent leakage current between two MOS transistors.
With respect to Claim 22, Nakazawa discloses (Fig. 1) wherein the polysilicon isolation structure, and the insulator liner share a common height
With respect to Claim 24, Hong teaches (Fig 1-7) wherein the (111) planar surface directly contacts the polysilicon isolation structure at a recess in the bottom of the polysilicon isolation structure
With respect to Claim 26, Nakazawa discloses (Fig. 1) further comprising: an additional insulator liner separating an additional sidewall of the polysilicon isolation structure from the substrate. Additionally, Hong teaches (Fig 1-7) wherein the semiconductor facet has an additional surface sharing a common edge with the (111) planar surface of the semiconductor facet and extending downward from the common edge to a bottom surface of the additional insulator liner.
Claims 27 are rejected under 35 U.S.C. 103 as being unpatentable over Nakazawa (US 2004/0026746) in view of Hong (CN 104425520) and in further view of Gruber (US 2018/0218939).
With respect to Claim 27, Nakazawa in view of Hong teaches most aspects of the present invention. Nakazawa discloses (Fig. 1) further comprising: a semiconductor device (transistor 22a,22b) overlying the top surface of the substrate. However, the combination of references do not show wherein the polysilicon isolation structure, and the insulator liner laterally extend in individual closed paths continuously around the semiconductor device.
On the other hand, and in the same field of endeavor, Gruber teaches (Fig 1-4) an integrated chip, comprising a polysilicon isolation structure (trench 320 comprising layer 322) extending into a top surface of a substrate, an insulator liner (321) lateral separating a sidewall of the polysilicon isolation structure from the substrate, wherein the polysilicon isolation structure and the insulator liner laterally extend in individual closed paths continuously around a semiconductor region (120) comprising an active device. Gruber teaches the trench rings may define isolated/floating regions comprising silicon and/or poly silicon fill for isolating regions in the device.
Therefore, it would have been obvious at the time the invention to one having ordinary skill in the art, or before the effective filing date of the invention to have wherein the polysilicon isolation structure and the insulator liner laterally extend in individual closed paths continuously around the semiconductor device as taught by Gruber, in the device of Nakazawa, because the trench rings may define isolated/floating regions comprising silicon and/or poly silicon fill for isolating regions in the device.
Claims 28-34 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2018/0358258) in view of Hong (CN 104425520)
With respect to Claim 28, Lee discloses (Fig. 3A-3B) most aspects of the current invention including an integrated chip, comprising:
a semiconductor-on-insulator (SOl) substrate comprising a base semiconductor layer (105a), a dielectric layer (105b) overlying the base semiconductor layer, and an active semiconductor layer (105c) overlying the dielectric layer
a polysilicon isolation structure (118) extending through the active semiconductor layer and the dielectric layer into the base semiconductor layer,
However, Lee does not show wherein the base semiconductor layer comprises a protrusion protruding upward to and culminating in a point, which is recessed into a bottom of the polysilicon isolation structure and at an elevation that is closer to an elevation at a bottom surface of the dielectric layer than to an elevation at a top surface of the dielectric layer.
On the other hand, and in the same field of endeavor, Hong teaches (Fig 1-7) an integrated chip, comprising a base semiconductor layer (100), a polysilicon isolation structure (125) extended into the base semiconductor layer, wherein the base semiconductor layer comprises a protrusion (facet/opening 122; see Fig 5) protruding upward to and culminating in a point, which is recessed into a bottom of the polysilicon isolation structure. Furthermore, Hong teaches the elevation of the protrusion protruding upward is at an elevation that is closer to the bottom of polysilicon isolation structure than to an elevation at a top surface of the polysilicon isolation structure. Hong teaches the semiconductor facet is formed at a depth deeper than the depth of the groove, to make the bottom of said source/drain leakage current of semiconductor substrate 100 through required path becomes longer, thereby reducing the adjacent leakage current between two MOS transistors
Accordingly, one of ordinary skill in the art would have known to have the protrusion at an elevation that is closer to an elevation at a bottom surface of the dielectric layer than to an elevation at a top surface of the dielectric layer in the device of Lee to implement a protrusion protruding upward to and culminating in a point, which is recessed into a bottom of the polysilicon isolation structure, as it has been held by the court that a prima facie case of obviousness exists in the case where all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. See in re KSR Int’l Co. v. Teleflex Inc, 550 U.S. at 416, 82 USPQ2d at 1395.
Therefore, it would have been obvious at the time the invention to one having ordinary skill in the art, or before the effective filing date of the invention to have wherein the base semiconductor layer comprises a protrusion protruding upward to and culminating in a point, which is recessed into a bottom of the polysilicon isolation structure and at an elevation that is closer to an elevation at a bottom surface of the dielectric layer than to an elevation at a top surface of the dielectric layer as taught by Hong, in the device of Lee, because the semiconductor facet is formed at a depth deeper than the depth of the groove, to make the bottom of said source/drain leakage current of semiconductor substrate 100 through required path becomes longer, thereby reducing the adjacent leakage current between two MOS transistors.
With respect to Claim 29, Lee in view of Hong, discloses wherein the point may be formed to an elevated level with the dielectric layer.
With respect to Claim 30, Lee discloses (Fig. 3A-3B) wherein the active semiconductor layer and the dielectric layer respectively have a first sidewall and a second sidewall, wherein the second sidewall has a top edge underlying and contacting a bottom edge of the first sidewall to form a common sidewall facing the polysilicon isolation structure and the protrusion.
With respect to Claim 31, Lee discloses (Fig. 3A-3B) wherein the base semiconductor layer has a third sidewall with a top edge underlying and contacting a bottom edge of the second sidewall to further form the common sidewall
With respect to Claim 32, Lee discloses (Fig. 3A-3B) wherein the base semiconductor layer, the dielectric layer, and the active semiconductor layer share a common width.
With respect to Claim 33, Lee discloses (Fig. 2,3A-3B) further comprising: a semiconductor device overlying the SOI substrate and laterally surrounded by the polysilicon isolation structure, wherein the semiconductor device comprises a gate dielectric layer (222) and a gate electrode (221) that overlie each individual layer of the SOI substrate.
With respect to Claim 34, Lee discloses (Fig. 2,3A-3B) further comprising: a pair of isolation liners (114) between which the polysilicon isolation structure is laterally arranged, wherein the pair of isolation liners laterally separate sidewalls of the polysilicon isolation structure from the SOI substrate and have individual bottommost edges level with a bottommost edge of the polysilicon isolation structure
Claims 35-37, 39-40 are rejected under 35 U.S.C. 103 as being unpatentable over Gruber (US 2018/0218939) in view of Hong (CN 104425520)
With respect to Claim 35, Gruber discloses (Fig. 1-4) most aspects of the current invention including an integrated chip, comprising:
a semiconductor region (120) for an active device on a substrate
a first polysilicon isolation structure (trench 320 comprising layer 322) inset into the substrate and extending laterally in a first closed path around the semiconductor region;
a second polysilicon isolation structure (trench 330 comprising layer 332) inset into the substrate and extending laterally in a second closed path around the first polysilicon isolation structure
Furthermore, although Gruber does not show a semiconductor device over a substrate, Gruber discloses the semiconductor region is an area to provide an active device on the substrate. However, Gruber does not show wherein the substrate has a first semiconductor facet structure and a second semiconductor facet structure that respectively underlie and are recessed into the first and second polysilicon isolation structures and that each decrease in width respectively into the first and second polysilicon isolation structures, and wherein the substrate has a single semiconductor material continuously from a top of the first semiconductor facet structure to a top of the second semiconductor facet structure.
On the other hand, and in the same field of endeavor, Hong teaches (Fig 1-7) an integrated chip, comprising a semiconductor device (110) over a substrate (100), a first polysilicon isolation structure (125 left) and a second polysilicon isolation structure (125 right), and a first semiconductor facet structure (opening 122 left; see Fig 5) and a second semiconductor facet structure (opening 122 right; see Fig 5) that respectively underlie and are recessed into the first and second polysilicon isolation structures and that each decrease in width respectively into the first and second polysilicon isolation structures, wherein the substrate has a single semiconductor material continuously from a top of the first semiconductor facet structure to a top of the second semiconductor facet structure. Hong teaches the semiconductor facets are formed at a depth deeper than the depth of the groove, to make the bottom of said source/drain leakage current of semiconductor substrate 100 through required path becomes longer, thereby reducing the adjacent leakage current between two MOS transistors.
Therefore, it would have been obvious at the time the invention to one having ordinary skill in the art, or before the effective filing date of the invention to have a semiconductor device, wherein the substrate has a first semiconductor facet structure and a second semiconductor facet structure that respectively underlie and are recessed into the first and second polysilicon isolation structures and that each decrease in width respectively into the first and second polysilicon isolation structures, and wherein the substrate has a single semiconductor material continuously from a top of the first semiconductor facet structure to a top of the second semiconductor facet structure as taught by Hong, in the device of Gruber, because the semiconductor facets are formed at a depth deeper than the depth of the groove, to make the bottom of said source/drain leakage current of semiconductor substrate 100 through required path becomes longer, thereby reducing the adjacent leakage current between two MOS transistors.
With respect to Claim 36, Hong teaches (Fig 1-7) wherein the first semiconductor facet structure decreases linearly in width into a bottom of the first polysilicon isolation structure
With respect to Claim 37, Hong teaches (Fig 1-7) further comprising: a dielectric liner (121) having a top surface level with a top surface of the substrate and laterally between the first polysilicon isolation structure and the substrate, wherein the first semiconductor facet structure has a sidewall slanting upward into a bottom of the first polysilicon isolation structure from a bottom surface of the dielectric liner
With respect to Claim 39, Hong teaches (Fig 1-7) wherein the first semiconductor facet structure has a slanted sidewall extending upward from a bottommost edge of the first polysilicon isolation structure, and wherein the slanted sidewall of the first polysilicon isolation structure has a plurality of indents and is at an acute angle with respect to a bottom surface of the substrate
With respect to Claim 40, Hong teaches (Fig 1-7) wherein a bottom of the first polysilicon isolation structure has a recess receiving the first semiconductor facet structure and having a profile matching a profile of the first semiconductor facet structure.
Claim 38 is rejected under 35 U.S.C. 103 as being unpatentable over Gruber (US 2018/0218939) in view of Hong (CN 104425520) and in further view of Graimann (US 6,207,494)
With respect to Claim 38, Gruber in view of Hong discloses most aspects of the current invention including. However, the combination of references do not show wherein a top surface of the polysilicon isolation structure is recessed relative to the top surface of the substrate.
On the other hand, and in the same field of endeavor, Graimann teaches (Fig. 15) an integrated chip comprising a substrate (layers 10,12,14,16), a polysilicon isolation structure (30) inset into the substrate, wherein a top surface of the polysilicon isolation structure is recessed relative to the top surface of the substrate. Graimann teaches doing so to provide a low contact resistance at the interface of the polysilicon isolation structure and a subsequent conductive material formed above the polysilicon isolation structure (column 11 lines 39-43).
Therefore, it would have been obvious at the time the invention to one having ordinary skill in the art, or before the effective filing date of the invention to have wherein a top surface of the polysilicon isolation structure is recessed relative to the top surface of the substrate as taught by Graimann, in the device of Gruber in view of Hong, to provide a low contact resistance at the interface of the polysilicon isolation structure and a subsequent conductive material formed above the polysilicon isolation structure.
Allowable Subject Matter
Claims 23 and 25 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUINTON A BRASFIELD whose telephone number is (571)272-0804. The examiner can normally be reached M-F 9AM-6PM.
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/Q.A.B/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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