DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-8, 10, and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung et al. (US 2018/0174970 A1; hereinafter Hung).
Regarding claim 1, Hung discloses a semiconductor structure (Fig. 1 of Hung; “FIG. 1 illustrates a top view of a semiconductor device” (¶ 0008 of Hung, emphasis added)), comprising:
a metal gate structure1 (a combination of (1) “work function metal layer 40” within “gate structure[s] 22 24”2 (¶ 0018) shown in Fig. 7 which is a “cross-section [of the] semiconductor device . . . in FIG. 1” (¶ 0009) and (2) “a high-k dielectric layer 38” within “gate structure[s] 22, 24” (¶ 0018) also shown in Fig. 7) including a gate dielectric layer (“high-k dielectric layer 38”3 (¶ 0018)) and a gate electrode (“metal layer 40”4 (¶ 0018)), the gate electrode including at least a first metal (the first metal being aluminum (“work function metal layer 40 . . . may include titanium aluminide (TiAl)”; ¶ 0020 of Hung));
a conductive layer5 (a combination of (1) “the low-resistance metal layer 42” within “gate structure[s] 22, 24” (¶ 0018) shown in Fig. 7 and (2) “barrier layer 58” which is formed of conductive metal (¶ 0024) over Hung’s gate structures 22, 24 shown in Fig. 7) formed on the gate electrode (as seen in Fig. 7, both components 42 and 58 of the conductive layer of Hung are formed over gate electrode 40 of Hung; as such, the conductive layer of Hung is considered to be ‘on’ the gate electrode), the conductive layer extending from a position below a top surface of the metal gate structure (“a top surface” being the upper surface of 406 within Hung’s components 22, 24 which directly contacts component 58; see annotated copy of Fig. 7, below. Further, as seen in Fig. 7, the bottommost portion of component 42 is below the cited top surface of the metal gate structure) to a position above the top surface of the metal gate structure (as seen in Fig. 7, the topmost portion of component 42 is above the cited top surface of the metal gate structure), the conductive layer includes at least the first metal (“low-resistance metal layer 42 may include . . . titanium aluminum (TiAl)”; ¶ 0020) and a second metal (titanium) different from the first metal; and
a gate contact (“metal layer 60” (¶ 0024) above Hung’s components 22, 24 shown in Fig. 7) disposed on the conductive layer (see Fig. 7),
wherein the gate dielectric layer includes a first sidewall (sidewall furthest along the down direction in Fig. 1) and a second sidewall (sidewall furthest along the up direction in Fig. 1) opposing the first sidewall, wherein the gate dielectric layer extends continuously from the first sidewall to the second sidewall, wherein laterally the conductive layer is fully between the first and second sidewalls of the gate dielectric layer (as no portion extends past the first and second sidewalls, the conductive layer is fully between the sidewalls).
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Regarding claim 2, Hung discloses the semiconductor structure of claim 1, as discussed above. Hung further discloses wherein the conductive layer is free of contact (i.e., not in direct contact) with gate dielectric layer (see Fig. 7).
Regarding claim 3, Hung discloses the semiconductor structure of claim 1, as discussed above. Hung further discloses wherein the conductive layer is in contact (although not direct contact) and laterally bounded by the gate dielectric layer (see Fig. 7).
Regarding claim 7, Hung discloses the semiconductor structure of claim 1, as discussed above. Hung further discloses that the conductive layer further includes a metallic film (“barrier layer 58” (¶ 0024 of Hung) which, as discussed in the rejection of claim 1, is part of the conductive layer) essentially of the second metal (as discussed in the rejection of claim 1, the second metal is titanium. Hung discloses that the metallic film may be titanium (“the barrier layer 58 is selected from the group consisting of Ti . . .”; ¶ 0024), and wherein the gate contact is in contact with the metallic film (see Fig. 7).
Regarding claim 10, Hung discloses the semiconductor structure of claim 1, as discussed above. Hung further discloses that the gate contact is in contact with both the conductive layer and the top surface of the metal gate structure (see Fig. 7).
Regarding claim 17, Hung discloses a semiconductor structure (Fig. 1 of Hung; “FIG. 1 illustrates a top view of a semiconductor device” (¶ 0008 of Hung, emphasis added)), comprising:
a metal gate structure7 (a combination of (1) “work function metal layer 40” within “gate structure[s] 22 24”8 (¶ 0018) shown in Fig. 7 which is a “cross-section [of the] semiconductor device . . . in FIG. 1” (¶ 0009) and (2) “a high-k dielectric layer 38” within “gate structure[s] 22, 24” (¶ 0018) also shown in Fig. 7) including a gate dielectric layer (“high-k dielectric layer 38”9 (¶ 0018)) and a gate electrode (“metal layer 40”10 (¶ 0018));
a conductive layer11 (a combination of (1) “the low-resistance metal layer 42” within “gate structure[s] 22, 24” (¶ 0018) shown in Fig. 7 and (2) the portion of “barrier layer 58” directly contacting the bottom surface of 60 which is formed of conductive metal (¶ 0024) over Hung’s gate structures 22, 24 shown in Fig. 7) deposited on and in contact with the gate electrode (as seen in Fig. 7, both components 42 and 58 of the conductive layer of Hung are formed over gate electrode 40 of Hung; as such, the conductive layer of Hung is considered to be ‘on’ and ‘in contact with’ the gate electrode), wherein the conductive layer has a wavy top surface (see Fig. 7), wherein the wavy top surface of the conductive layer is above a topmost surface of the metal gate structure (See Fig. 7); and
a gate contact (“metal layer 60” (¶ 0024) above Hung’s components 22, 24 shown in Fig. 7) landing on the wavy top surface of the conductive layer (see Fig. 7), wherein a bottom surface of the gate contact is above a topmost surface of the conductive layer (see Fig. 7).
Regarding claim 18, Hung discloses the semiconductor structure of claim 17, as discussed above. Hung further discloses wherein the conductive layer as a whole is laterally bounded by the gate dielectric layer (see Fig. 7).
Regarding claim 19, Hung discloses the semiconductor structure of claim 17, as discussed above. Hung further discloses wherein the conductive layer includes a first metal (the first metal being aluminum, “low-resistance metal layer 42 may include . . . titanium aluminum (TiAl)”; ¶ 0020) and a second metal (aluminum) different from the first metal, and wherein the gate electrode includes the first metal and is substantially free of the second metal (“zirconium aluminide”, ¶ 0020).
Regarding claim 20, Hung discloses the semiconductor structure of claim 17, as discussed above. Hung further discloses wherein the conductive layer extends vertically from a position below the topmost surface of the metal gate structure to a position above the topmost surface of the metal gate structure (See Fig. 7).
Alternatively regarding claim 112, Hung discloses a semiconductor structure (Fig. 1 of Hung; “FIG. 1 illustrates a top view of a semiconductor device” (¶ 0008 of Hung, emphasis added)), comprising:
a metal gate structure13 (a combination of (1) “work function metal layer 40” within “gate structure[s] 22, 24”14 (¶ 0018) shown in Fig. 7 which is a “cross-section [of the] semiconductor device . . . in FIG. 1” (¶ 0009); (2) “a high-k dielectric layer 38” within “gate structure[s] 22, 24” (¶ 0018) also shown in Fig. 7; and (3) “gate dielectric layer 26” within “gate structure[s] 22, 24” (¶ 0018) also shown in Fig. 7) including a gate dielectric layer (26) and a gate electrode (40), the gate electrode including at least a first metal (the first metal being aluminum (“work function metal layer 40 . . . may include titanium aluminide (TiAl)”; ¶ 0020 of Hung));
a conductive layer15 (a combination of (1) “the low-resistance metal layer 42” within “gate structure[s] 22, 24” (¶ 0018) shown in Fig. 7 and (2) “barrier layer 58” which is formed of conductive metal (¶ 0024) over Hung’s gate structures 22, 24 shown in Fig. 7) formed on the gate electrode (as seen in Fig. 7, both components 42 and 58 of the conductive layer of Hung are formed over gate electrode 40 of Hung; as such, the conductive layer of Hung is considered to be ‘on’ the gate electrode), the conductive layer extending from a position below a top surface of the metal gate structure (“a top surface” being the upper surface of 4016 within Hung’s components 22, 24 which directly contacts component 58; see annotated copy of Fig. 7, below. Further, as seen in Fig. 7, the bottommost portion of component 42 is below the cited top surface of the metal gate structure) to a position above the top surface of the metal gate structure (as seen in Fig. 7, the topmost portion of component 42 is above the cited top surface of the metal gate structure), the conductive layer includes at least the first metal (“low-resistance metal layer 42 may include . . . titanium aluminum (TiAl)”; ¶ 0020) and a second metal (titanium) different from the first metal; and
a gate contact (“metal layer 60” (¶ 0024) above Hung’s components 22, 24 shown in Fig. 7) disposed on the conductive layer (see Fig. 7),
wherein the gate dielectric layer includes a first sidewall (sidewall furthest along the down direction in Fig. 1) and a second sidewall (sidewall furthest along the up direction in Fig. 1) opposing the first sidewall, wherein the gate dielectric layer extends continuously from the first sidewall to the second sidewall, wherein laterally the conductive layer is fully between the first and second sidewalls of the gate dielectric layer (as no portion extends past the first and second sidewalls, the conductive layer is fully between the sidewalls).
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Regarding claim 4, Hung discloses the semiconductor structure of claim 1, as discussed in the alternative rejection of claim 1, above. Hung further discloses wherein the metal gate structure includes a capping layer (“high-k dielectric layer 38”17 (¶ 0018)) interposing the gate dielectric layer and the gate electrode, and wherein the conductive layer covers a top surface of the capping layer (see Fig. 7).
Alternatively regarding claim 118, Hung discloses a semiconductor structure (Fig. 1 of Hung; “FIG. 1 illustrates a top view of a semiconductor device” (¶ 0008 of Hung, emphasis added)), comprising:
a metal gate structure19 (a combination of (1) “work function metal layer 40” within “gate structure[s] 22, 24”20 (¶ 0018) shown in Fig. 7 which is a “cross-section [of the] semiconductor device . . . in FIG. 1” (¶ 0009); (2) “a high-k dielectric layer 38” within “gate structure[s] 22, 24” (¶ 0018) also shown in Fig. 7; and (3) “gate dielectric layer 26” within “gate structure[s] 22, 24” (¶ 0018) also shown in Fig. 7) including a gate dielectric layer (26) and a gate electrode (40), the gate electrode including at least a first metal (the first metal being aluminum (“work function metal layer 40 . . . may include titanium aluminide (TiAl)”; ¶ 0020 of Hung));
a conductive layer21 (a combination of (1) “the low-resistance metal layer 42” within “gate structure[s] 22, 24” (¶ 0018) shown in Fig. 7 and (2) “barrier layer 58” which is formed of conductive metal (¶ 0024) over Hung’s gate structures 22, 24 shown in Fig. 7) formed on the gate electrode (as seen in Fig. 7, both components 42 and 58 of the conductive layer of Hung are formed over gate electrode 40 of Hung; as such, the conductive layer of Hung is considered to be ‘on’ the gate electrode), the conductive layer extending from a position below a top surface of the metal gate structure (“a top surface” being the upper surface of 4022 within Hung’s components 22, 24 which directly contacts component 58; see annotated copy of Fig. 7, below. Further, as seen in Fig. 7, the bottommost portion of component 42 is below the cited top surface of the metal gate structure) to a position above the top surface of the metal gate structure (as seen in Fig. 7, the topmost portion of component 42 is above the cited top surface of the metal gate structure), the conductive layer includes at least the first metal and a second metal different from the first metal (a combination of copper and aluminum; “low-resistance metal layer 42 may include copper (Cu), aluminum (Al) . . . or any combination thereof”23; ¶ 0020); and
a gate contact (“metal layer 60” (¶ 0024) above Hung’s components 22, 24 shown in Fig. 7) disposed on the conductive layer (see Fig. 7),
wherein the gate dielectric layer includes a first sidewall (sidewall furthest along the down direction in Fig. 1) and a second sidewall (sidewall furthest along the up direction in Fig. 1) opposing the first sidewall, wherein the gate dielectric layer extends continuously from the first sidewall to the second sidewall, wherein laterally the conductive layer is fully between the first and second sidewalls of the gate dielectric layer (as no portion extends past the first and second sidewalls, the conductive layer is fully between the sidewalls).
Regarding claim 6, Hung discloses the semiconductor structure of claim 1, as discussed in the second alternative rejection of claim 1 above. Hung further discloses that the first metal is aluminum (see discussion of the first metal in the second alternative rejection of claim 1, above) and that the second metal is copper (see discussion of the second metal in the second alternative rejection of claim 1, above).
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Alternatively regarding claim 1, Hung discloses a semiconductor structure (Fig. 1 of Hung; “FIG. 1 illustrates a top view of a semiconductor device” (¶ 0008 of Hung, emphasis added)), comprising:
a metal gate structure24 (a combination of (1) “work function metal layer 40” within “gate structure[s] 22 24”25 (¶ 0018) shown in Fig. 7 which is a “cross-section [of the] semiconductor device . . . in FIG. 1” (¶ 0009) and (2) “a high-k dielectric layer 38” within “gate structure[s] 22, 24” (¶ 0018) also shown in Fig. 7) including a gate dielectric layer (“high-k dielectric layer 38”26 (¶ 0018)) and a gate electrode (“metal layer 40”27 (¶ 0018)), the gate electrode including at least a first metal (the first metal being aluminum (“work function metal layer 40 . . . may include . . . tantalum aluminide (TaAl)”; ¶ 0020 of Hung));
a conductive layer28 (a combination of (1) “the low-resistance metal layer 42” within “gate structure[s] 22, 24” (¶ 0018) shown in Fig. 7; (2) “barrier layer 58” which is formed of conductive metal (¶ 0024) over Hung’s gate structures 22, 24 shown in Fig. 7; and (3) the “optional barrier layer (not shown)” (¶ 0020)) formed on the gate electrode (as seen in Fig. 7, both components 42 and 58 of the conductive layer of Hung are formed over gate electrode 40 of Hung; as such, the conductive layer of Hung is considered to be ‘on’ the gate electrode), the conductive layer extending from a position below a top surface of the metal gate structure (“a top surface” being the upper surface of 4029 within Hung’s components 22, 24 which directly contacts component 58; see annotated copy of Fig. 7, below. Further, as seen in Fig. 7, the bottommost portion of component 42 is below the cited top surface of the metal gate structure) to a position above the top surface of the metal gate structure (as seen in Fig. 7, the topmost portion of component 42 is above the cited top surface of the metal gate structure), the conductive layer includes at least the first metal (“low-resistance metal layer 42 may include . . . titanium aluminum (TiAl)”; ¶ 0020) and a second metal (titanium) different from the first metal; and
a gate contact (“metal layer 60” (¶ 0024) above Hung’s components 22, 24 shown in Fig. 7) disposed on the conductive layer (see Fig. 7),
wherein the gate dielectric layer includes a first sidewall (sidewall furthest along the down direction in Fig. 1) and a second sidewall (sidewall furthest along the up direction in Fig. 1) opposing the first sidewall, wherein the gate dielectric layer extends continuously from the first sidewall to the second sidewall, wherein laterally the conductive layer is fully between the first and second sidewalls of the gate dielectric layer (as no portion extends past the first and second sidewalls, the conductive layer is fully between the sidewalls).
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Regarding claim 8, Hung discloses the semiconductor structure of claim 1, as discussed in the third alternative rejection of claim 1 above. Hung further discloses that the gate electrode includes a third metal (tantalum; as discussed in the second alternative rejection of claim 1, above, the gate electrode 40 of Hung comprises TaAl (¶ 0020 of Hung)) different from either the first metal or the second metal, and the conductive layer includes a center portion (42, which is the center of the alloy layer) rich of the first metal (as discussed in the second alternative rejection of claim 1, above, component 42 comprises TiAl, which is 50% aluminum which is interpreted as being ‘rich’ of aluminum) and a side portion (the optional barrier layer is formed between components 40 and 42 in Fig. 7 (¶ 0020) and, therefore, forms the side of the conductive layer) rich of the third metal (¶ 0020).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2018/0174970 A1; hereinafter Hung) as applied to claim 130, above, and further in view of Lei et al. (US 2013/0221445 A1).
Regarding claim 4, Hung discloses the semiconductor structure of claim 1, as discussed in the first rejection of claim 1 above. This mapping of Hung does not include a capping layer as claimed. However, it was well known in the art to form a capping layer (“high-k dielectric cap layer”, ¶ 0024 of Lei) on high-k dielectric layers.
There was a benefit to forming capping layers in that it serves as an effective aluminum barrier (¶ 0024 of Lei). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form a capping layer as taught by Lei on the gate dielectric layer of Hung for this benefit.
In the resulting configuration, the capping layer interposes the gate dielectric layer and the gate electrode and the conductive layer covers a top surface of the capping layer (see Fig. 7 of Hung).
Regarding claim 5, the combination of Hung and Lei discloses the semiconductor structure of claim 4, as discussed above. Lei further discloses wherein the capping layer includes titanium silicon nitride (¶ 0024).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung as applied to claim 131, above.
Regarding claim 9, Hung discloses the semiconductor structure of claim 1, as discussed above. Hung further discloses that the conductive layer includes a top portion (portion of 58 above the metal gate structure as shown in Fig. 7 of Hung) above the top surface of the metal gate structure (see Fig. 7) and a bottom portion (portion of 58 below the aforementioned top surface of the metal gate structure in Fig. 7) below the top surface of the metal gate structure (per definition).
Hung does not explicitly disclose the thicknesses of these portions to determine if the fall within the claimed range.
However, there was a benefit to forming the entirety of component 58 of Hung to have a substantially uniform thickness in that component 58 (which, as discussed above, functions as a barrier) would be of sufficient thickness to effectively act as a barrier to all of the components to which it is adjacent while minimizing the amount of material used (i.e., no thin spots which would result in degraded protection and no overly thick spots which would waste material).
It would have been obvious to one having ordinary skill in the art before the Application's effective filing date would have formed component 58 of Hung to have a uniform thickness for this benefit. As such, and as demonstrated in the annotated copy of Fig. 7, below, the ratio of a thickness of the top portion to a thickness of the bottom portion would be substantially 1:1; since 1:1 falls within the claimed range of about 1:8 to about 1.5:1, the range is anticipated (MPEP § 2131.03)).
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Allowable Subject Matter
Claims 11-16 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record does not disclose a semiconductor structure which satisfies all of the limitations of Applicant’s claim 11 which requires a non-conductive residue within the conductive layer wherein a concentration of the non-conductive residue in the conductive layer increases in a direction towards the gate electrode. Hung, the closest prior art of record, discloses a semiconductor structure which satisfies claim 1 (see any of the rejections of claim 1, above) but the conductive layer does not include a non-conductive residue, let alone a non-conductive residue in such a way that the concentration of the non-conductive residue increases in a direction toward the gate electrode. Further, it would not have been obvious to one having ordinary skill in the art before the Application's effective filing date to include such a non-conductive residue in the conductive layer of Hung as it would increase the complexity of the fabrication process and require the inclusion of additional materials.
Claims 12-16 depend from claim 11 and are allowed based on this dependency.
Response to Arguments
Applicant's arguments filed 9/30/2025 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant’s identification of what constitutes the sidewall of the gate dielectric layer Hung is not the only portion of the gate dielectric layer which may be considered a sidewall. As noted in the rejections above, other sidewalls of the gate dielectric layer of Hung satisfy all of the newly added claim limitations.
Regarding claim 17, the mapping of Hung has been changed to address the newly added limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A CULBERT/ Examiner, Art Unit 2815
1 The Examiner notes that ‘structure’, as the term is used by Applicant, does not require that it consists of only a single component but, instead, may consist of multiple distinct components. Further, the Examiner notes that “metal gate structure” does not require the structure to consist only of metals, as claim 1 requires the “metal gate structure” to also comprise a dielectric layer.
2 Figs. 1 and 7 of Hung show gate structures 20, 22, and 24 which have distinct configurations. This Office action will use gate structure 20 for reference.
3 Dielectric layer 38 of Hung is considered a “gate dielectric layer” as it is a dielectric layer in the gate structure between the gate electrode and underlying substrate 12 of Hung.
4 Although the text of Hung does not use the term ‘electrode’, metal layer 40 of Hung is a conductor within the gate structure used to establish electrical contact with the underlying substrate 12 of Hung and is, therefore, considered a “gate electrode”.
5 The Examiner notes that a “layer” is interpreted as allowing for the inclusion of a plurality of sub-layers.
6 The Examiner notes that this surface is a surface of an object that faces upwards and would be seen if looking down from directly above and, therefore, may be considered a “top surface”, even though it is not a “topmost surface”. Were Applicant to amend the claim to require this surface to be a “topmost surface”, this rejection would be overcome.
7 The Examiner notes that ‘structure’, as the term is used by Applicant, does not require that it consists of only a single component but, instead, may consist of multiple distinct components. Further, the Examiner notes that “metal gate structure” does not require the structure to consist only of metals, as claim 1 requires the “metal gate structure” to also comprise a dielectric layer.
8 Figs. 1 and 7 of Hung show gate structures 20, 22, and 24 which have distinct configurations. This Office action will use gate structure 20 for reference.
9 Dielectric layer 38 of Hung is considered a “gate dielectric layer” as it is a dielectric layer in the gate structure between the gate electrode and underlying substrate 12 of Hung.
10 Although the text of Hung does not use the term ‘electrode’, metal layer 40 of Hung is a conductor within the gate structure used to establish electrical contact with the underlying substrate 12 of Hung and is, therefore, considered a “gate electrode”.
11 The Examiner notes that a “layer” is interpreted as allowing for the inclusion of a plurality of sub-layers.
12This specific rejection of claim 10 will hereinafter be referenced as the “alternative rejection of claim 10”.
13 The Examiner notes that ‘structure’, as the term is used by Applicant, does not require that it consists of only a single component but, instead, may consist of multiple distinct components. Further, the Examiner notes that “metal gate structure” does not require the structure to consist only of metals, as, for example, claim 1 requires the “metal gate structure” to also comprise a dielectric layer.
14 Figs. 1 and 7 of Hung show gate structures 20, 22, and 24 which have distinct configurations. This Office action will use gate structure 20 for reference.
15 The Examiner notes that a “layer” is interpreted as allowing for the inclusion of a plurality of sub-layers.
16 The Examiner notes that this surface is a surface of an object that faces upwards and would be seen if looking down from directly above and, therefore, may be considered a “top surface”, even though it is not a “topmost surface”. Were Applicant to amend the claim to require this surface to be a “topmost surface”, this rejection would be overcome.
17 Dielectric layer 38 of Hung is considered a “capping layer” as it forms a cap on the gate dielectric layer of Hung.
18This specific rejection of claim 10 will hereinafter be referenced as the “alternative rejection of claim 10”.
19 The Examiner notes that ‘structure’, as the term is used by Applicant, does not require that it consists of only a single component but, instead, may consist of multiple distinct components. Further, the Examiner notes that “metal gate structure” does not require the structure to consist only of metals, as, for example, claim 1 requires the “metal gate structure” to also comprise a dielectric layer.
20 Figs. 1 and 7 of Hung show gate structures 20, 22, and 24 which have distinct configurations. This Office action will use gate structure 20 for reference.
21 The Examiner notes that a “layer” is interpreted as allowing for the inclusion of a plurality of sub-layers.
22 The Examiner notes that this surface is a surface of an object that faces upwards and would be seen if looking down from directly above and, therefore, may be considered a “top surface”, even though it is not a “topmost surface”. Were Applicant to amend the claim to require this surface to be a “topmost surface”, this rejection would be overcome.
23 Although Hung does not explicitly spell out a combination of copper and aluminum, a person of ordinary skill in the art, reading Hung, would at once envisage the claimed combination. (MPEP 2131.02(III) citing Kennametal, Inc. v. Ingersoll Cutting Tool Co., 780 F.3d 1376, 1381, 114 USPQ2d 1250, 1254 (Fed. Cir. 2015). “Kennametal addresses whether the disclosure of a limited number of combination possibilities discloses one of the possible combinations.” (MPEP 2131.02(III)) In Kennametal, the prior art disclosed five binding agents and three coating techniques, resulting in 3x5 = 15 possible combinations, one of which read upon the claim limitation. Similar to the facts of Kennametal, Hung discloses only 15 possible combinations for the alloy layer 42 (four individual options and “any combination thereof” yields fifteen total possible combinations which are, specifically, the four individual compositions of Cu, Al, TiAl, or CoWP (¶ 0020 of Hung); the six compositions consisting of exactly two materials of the four possible materials; the four compositions consisting of exactly three of the materials; and the one composition which consists of all four materials). As such, the disclosure of Hung anticipates a combination of copper and aluminum.
24 The Examiner notes that ‘structure’, as the term is used by Applicant, does not require that it consists of only a single component but, instead, may consist of multiple distinct components. Further, the Examiner notes that “metal gate structure” does not require the structure to consist only of metals, as claim 1 requires the “metal gate structure” to also comprise a dielectric layer.
25 Figs. 1 and 7 of Hung show gate structures 20, 22, and 24 which have distinct configurations. This Office action will use gate structure 20 for reference.
26 Dielectric layer 38 of Hung is considered a “gate dielectric layer” as it is a dielectric layer in the gate structure between the gate electrode and underlying substrate 12 of Hung.
27 Although the text of Hung does not use the term ‘electrode’, metal layer 40 of Hung is a conductor within the gate structure used to establish electrical contact with the underlying substrate 12 of Hung and is, therefore, considered a “gate electrode”.
28 The Examiner notes that a “layer” is interpreted as allowing for the inclusion of a plurality of sub-layers.
29 The Examiner notes that this surface is a surface of an object that faces upwards and would be seen if looking down from directly above and, therefore, may be considered a “top surface”, even though it is not a “topmost surface”. Were Applicant to amend the claim to require this surface to be a “topmost surface”, this rejection would be overcome.
30 i.e., the first rejection of claim 1, not either of the alternative rejections.
31 i.e., the first rejection of claim 1, not either of the alternative rejections.