DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8 and 16-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. 11,469,197. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations recited in claims 1-8 and 16-20 of the present invention are recited within claims 1-7 of U.S. Patent No. 11,469,197.
Present invention (18/781,022)
U.S. Patent No. 11,469,197 (reference)
Claim 1: A method comprising:
bonding a first integrated circuit die and a second integrated circuit die to a substrate with dielectric-to-dielectric bonds and with metal-to-metal bonds (see claim 1, lines 46-50 of U.S. Patent No. 11,469,197, “an interposer” can be also “a substrate”, as claimed);
forming a stress reduction material around the first integrated circuit die and the second integrated circuit die, the stress reduction material having a first Young's modulus (see claim 1, lines 51-54 of U.S. Patent No. 11,469,197);
encapsulating the stress reduction material, the first integrated circuit die, and the second integrated circuit die with a molding material (see claim 1, lines 55-57 of U.S. Patent No. 11,469,197),
the molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus (see claim 1, lines 57-59 of U.S. Patent No. 11,469,197);
and thinning the molding material (see claim 1, line 60 of U.S. Patent No. 11,469,197).
Claim 1: “A method comprising:
bonding a first integrated circuit device and a second integrated circuit device to an interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds”;
forming a stress reduction material around the first integrated circuit device and the second integrated circuit device, the stress reduction material having a first Young's modulus;
encapsulating the stress reduction material, the first integrated circuit device, and the second integrated circuit device with a molding material,
the molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus;
and thinning the molding material…”.
Claim 2: The method of claim 1, wherein thinning the molding material exposes the stress reduction material (see claim 1, lines 60-62 of U.S. Patent No. 11,469,197, when the first and second integrated circuit devices are exposed, the stress reduction material is also inherently exposed after thinning).
Claim 1:
“…thinning the molding material to expose the first integrated circuit device and the second integrated circuit device”.
Claim 3: The method of claim 1, wherein the stress reduction material comprises a polymer material and a filler (see claims 2 and 3, lines 63-53 & 1-2 of U.S. Patent No. 11,469,197).
Claims 2 and 3: “wherein the stress reduction material comprises a first polymer material…” (claim 2), “wherein the stress reduction material further comprises first fillers…” (claims 3).
Claim 4: The method of claim 3, wherein the stress reduction material further comprises a surfactant (see claim 4 of U.S. Patent No. 11,469,197).
Claim 4: The method of claim 2, “wherein the stress reduction material further comprises a surfactant”.
Claim 5: The method of claim 3, wherein the polymer material is an epoxy, a polyimide-based material, a benzocyclobutene-based material, a silicone material, or an acrylic material (see claim 5 of U.S. Patent No. 11,469,197.
Claim 5: The method of claim 2, “wherein the first polymer material is a first epoxy, a polyimide-based material, a benzocyclobuten (BCB) based material, a silicone material, or an acrylic material…”
Claim 6. The method of claim 1, wherein the stress reduction material has fillet portions and the fillet portions are exposed after thinning the molding material (see claim 6 of U.S. Patent No. 11,469,197).
Claim 6. The method of claim 1, “wherein the stress reduction material has …fillet portions, …wherein the fillet portions are exposed after thinning the molding material”.
Claim 7: The method of claim 1, wherein the stress reduction material has fillet portions and the fillet portions remain covered after thinning the molding material (see claim 7 of U.S. Patent No. 11,469,197)
Claim 7: The method of claim 1, “wherein the stress reduction material has …fillet portions, … and wherein the fillet portions remain covered after thinning the molding material”.
Claim 8: The method of claim 1, wherein the substrate is an interposer (see claim 1, lines 46-49 of U.S. Patent No. 11,469,197).
Claim 1: “bonding a first integrated circuit device and a second integrated circuit device to an interposer…”
Claim 16: A method comprising: bonding a first integrated circuit die to a substrate with dielectric-to-dielectric bonds and with metal-to-metal bonds (see claim 1, lines 46-50 of U.S. Patent No. 11,469,197);
forming a stress reduction material around the first integrated circuit die, the stress reduction material having a first Young’s modulus (see claim 1, lines 51-54 of U.S. Patent No. 11,469,197);
encapsulating the stress reduction material and the first integrated circuit die with a molding material, the molding material having a second Young’s modulus (see claim 1, lines 55-58 of U.S. Patent No. 11,469,197),
the first Young’s modulus less than the second Young’s modulus; and thinning the molding material (see claim 1, lines 58-60 of U.S. Patent No. 11,469,197).
Claim 1: “A method comprising: “bonding a first integrated circuit device … to an interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds;
forming a stress reduction material around the first integrated circuit device,… the stress reduction material having a first Young's modulus;
encapsulating the stress reduction material, the first integrated circuit device, …with a molding material, the molding material having a second Young's modulus,
the first Young's modulus less than the second Young's modulus; and thinning the molding material...”
Claim 17: The method of claim 16, wherein the stress reduction material extends partially up sidewalls of the first integrated circuit die (see claim 1, lines 51-52 of U.S. Patent No. 11,469,197, because a stress reduction material is formed around the first integrated circuit device, the stress reduction material necessarily extends at least partially along the sidewalls of the first integrated circuit die).
Claim 1: “…forming a stress reduction material around the first integrated circuit device…”.
Claim 18: The method of claim 16, wherein the stress reduction material extends completely up sidewalls of the first integrated circuit die (see claim 1, lines 51-52 of U.S. Patent No. 11,469,197, because a stress reduction material is formed around the first integrated circuit device, the stress reduction material necessarily extends completely along the sidewalls of the first integrated circuit die).
Claim 1: “…forming a stress reduction material around the first integrated circuit device…”.
Claim 19: The method of claim 16, wherein thinning the molding material exposes the first integrated circuit die (see claim 1, lines 60-62 of U.S. Patent No. 11,469,197).
Claim 1: “…thinning the molding material to expose the first integrated circuit device …”.
Claim 20: The method of claim 16, wherein the substrate comprises through-substrate vias that are electrically coupled to the first integrated circuit die (see claim 1, lines 46-50, “bonding a first integrated circuit device … to an interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds” inherently comprising an interposer/substrate that includes through-substrate vias so that the interposer/substrate can electrically connect to the first integrated circuit device to enable functionality within the device package).
Claim 1: “bonding a first integrated circuit device …to an interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds…”.
Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,469,197 in view of Chen et al. (U.S 2020/0006324 A1).
As to claim 9, as applied to claim 1 above, claim 1 of U.S. Patent No. 11,469,197 disclose all claimed limitations recited in claim 1 of the present invention except for the limitation: wherein the substrate is a third integrated circuit die.
Chen et al. disclose in Fig. 1 a method comprising: bonding a first and second dies (200, 300) to a substrate (100), wherein the substrate (“die” 100) is a third integrated circuit die (see Fig. 1, para. [0034]-[0039]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify the claim of U.S. Patent No. 11,469,197 to include a substrate that is a third integrated circuit die as taught by Chen et al., in order to provide structural support for the first and second dies while simultaneously integrating additional functionality within the packaged device.
Claims 1-8 and 16-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. 11,817,410. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations recited in claims 1-8 and 16-20 of the present invention are recited within claims 1-7 of U.S. Patent No. 11,817,410.
Present invention (18/781,022)
U.S. Patent No. 11,817,410 (reference)
Claim 1: A method comprising:
bonding a first integrated circuit die and a second integrated circuit die to a substrate with dielectric-to-dielectric bonds and with metal-to-metal bonds (see claim 1, lines 46-52 of U.S. Patent No. 11,817,410);
forming a stress reduction material around the first integrated circuit die and the second integrated circuit die, the stress reduction material having a first Young's modulus (see claim 1, lines 53-55 of U.S. Patent No. 11,817,410);
encapsulating the stress reduction material, the first integrated circuit die, and the second integrated circuit die with a molding material (see claim 1, lines 56-58 of U.S. Patent No. 11,817,410),
the molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus (see claim 1, lines 58-60 of U.S. Patent No. 11,817,410);
and thinning the molding material (see claim 6, lines 20-21 of U.S. Patent No. 11,817,410).
Claim 1 and 6: “A method comprising:
connecting a first integrated circuit device and a second integrated circuit device to a first side of an interposer, the first integrated circuit device connected to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds;
forming a stress reduction material around the first integrated circuit device and on the interposer, the stress reduction material having a first Young's modulus;
encapsulating the stress reduction material, the first integrated circuit device, and the second integrated circuit device with a molding material,
the molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus” (claim 1);
and “the method further comprising:
thinning the molding material” (claim 6)
Claim 2: The method of claim 1, wherein thinning the molding material exposes the stress reduction material (see claim 6, lines 15-16, 20-23 of U.S. Patent No. 11,817,410).
Claim 6: “wherein the stress reduction material has a gap portion and fillet portions… thinning the molding material to expose …the gap portion, and the fillet portions”.
Claim 3: The method of claim 1, wherein the stress reduction material comprises a polymer material (see claim 2 of U.S. Patent No. 11,817,410) and a filler (see claim 3 of U.S. Patent No. 11,817,410).
Claims 2 and 3: “wherein the stress reduction material comprises a first polymer material…” (claim 2), “wherein the stress reduction material further comprises first fillers…” (claims 3).
Claim 4: The method of claim 3, wherein the stress reduction material further comprises a surfactant (see claim 4 of U.S. Patent No. 11,817,410).
Claim 4: The method of claim 2, “wherein the stress reduction material further comprises a surfactant”.
Claim 5: The method of claim 3, wherein the polymer material is an epoxy, a polyimide-based material, a benzocyclobutene-based material, a silicone material, or an acrylic material (see claim 5 of U.S. Patent No. 11,817,410).
Claim 5: The method of claim 2, “wherein the first polymer material is a first epoxy, a polyimide-based material, a benzocyclobuten based material, a silicone material, or an acrylic material…”
Claim 6: The method of claim 1, wherein the stress reduction material has fillet portions and the fillet portions are exposed after thinning the molding material (see claim 6 of U.S. Patent No. 11,817,410).
Claim 6: The method of claim 1, “wherein the stress reduction material has …fillet portions, … thinning the molding material to expose …the fillet portions.”.
Claim 7: The method of claim 1, wherein the stress reduction material has fillet portions and the fillet portions remain covered after thinning the molding material (see claim 7 of U.S. Patent No. 11,817,410).
Claim 7: The method of claim 1, “wherein the stress reduction material has …fillet portions, … and wherein the fillet portions remain covered after thinning the molding material”.
Claim 8: The method of claim 1, wherein the substrate is an interposer (see claim 1 of U.S. Patent No. 11,817,410).
Claim 1: “A method comprising: connecting a first integrated circuit device and a second integrated circuit device to a first side of an interposer”.
Claim 16: A method comprising: bonding a first integrated circuit die to a substrate with dielectric-to-dielectric bonds and with metal-to-metal bonds (see claim 1, lines 47-52 of U.S. Patent No. 11,817,410);
forming a stress reduction material around the first integrated circuit die, the stress reduction material having a first Young’s modulus (see claim 1, lines 53-55 of U.S. Patent No. 11,817,410);
encapsulating the stress reduction material and the first integrated circuit die with a molding material, the molding material having a second Young’s modulus (see claim 1, lines 56-59 of U.S. Patent No. 11,817,410),
the first Young’s modulus less than the second Young’s modulus (see claim 1, lines 59-60 of U.S. Patent No. 11,817,410);
and thinning the molding material (see claim 6, lines 20-21 of U.S. Patent No. 11,817,410).
Claims 1 and 6: “A method comprising: connecting a first integrated circuit device …to a first side of an interposer, the first integrated circuit device connected to the
interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds;
forming a stress reduction material around the first integrated circuit device,… the stress reduction material having a first Young's modulus;
encapsulating the stress reduction material, the first integrated circuit device, …with a molding material, the molding material having a second Young's modulus,
the first Young's modulus less than the second Young's modulus (claim 1);
and thinning the molding material...” (claim 6).
Claim 17: The method of claim 16, wherein the stress reduction material extends partially up sidewalls of the first integrated circuit die (see claim 1, lines 53-55 of U.S. Patent No. 11,817,410, because a stress reduction material is formed around the first integrated circuit device, the stress reduction material necessarily extends at least partially along the sidewalls of the first integrated circuit die).
Claim 1: “…forming a stress reduction material around the first integrated circuit device…”.
Claim 18: The method of claim 16, wherein the stress reduction material extends completely up sidewalls of the first integrated circuit die (see claim 1, lines 53-54 of U.S. Patent No. 11,817,410, because a stress reduction material is formed around the first integrated circuit device, the stress reduction material necessarily extends completely along the sidewalls of the first integrated circuit die).
Claim 1: “…forming a stress reduction material around the first integrated circuit device…”.
Claim 19: The method of claim 16, wherein thinning the molding material exposes the first integrated circuit die (see claim 6, lines 20-22 of U.S. Patent No. 11,817,410).
Claim 6: “…thinning the molding material to expose the first integrated circuit device …”.
Claim 20: The method of claim 16, wherein the substrate comprises through-substrate vias that are electrically coupled to the first integrated circuit die (see claim 1, lines 46-52 of U.S. Patent No. 11,817,410 “the first integrated circuit device connected to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds” inherently comprising an interposer/substrate that includes through-substrate vias so that the interposer/substrate can electrically connect to the first integrated circuit device to enable functionality within the device package).
Claim 1: “connecting a first integrated circuit device …to a first side of an interposer… the first integrated circuit device connected to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds…”.
Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 6 of U.S. Patent No. 11,817,410 in view of Chen et al. (U.S 2020/0006324 A1).
As to claim 9, as applied to claim 1 above, claims 1 and 6 of U.S. Patent No. 11,817,410 disclose all claimed limitations recited in claim 1 of the present invention except for the limitation: wherein the substrate is a third integrated circuit die.
Chen et al. disclose in Fig. 1 a method comprising: bonding a first and second dies (200, 300) to a substrate (100), wherein the substrate (“die” 100) is a third integrated circuit die (see Fig. 1, para. [0034]-[0039]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify the claim of U.S. Patent No. 11,817,410 to include a substrate that is a third integrated circuit die as taught by Chen et al., in order to provide structural support for the first and second dies while simultaneously integrating additional functionality within the packaged device.
Allowable Subject Matter
Claims 10-15 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: a method comprising: attaching a first integrated circuit die to a substrate with dielectric-to-dielectric bonds and with metal-to-metal bonds; forming a first stress reduction material around a first edge of the first integrated circuit die, the first stress reduction material having a first Young's modulus; forming a second stress reduction material around a second edge of the first integrated circuit die, the second stress reduction material having a second Young's modulus, the second Young's modulus being different from the first Young's modulus; encapsulating the first stress reduction material, the second stress reduction material, and the first integrated circuit die with a molding material; and thinning the molding material, as recited in independent claim 10. Claims 11-15 are dependent upon independent claim 10 and are also allowed.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Thanh Y. Tran/Primary Examiner, Art Unit 2817 September 25, 2026
Prosecution Insights