Prosecution Insights
Last updated: August 17, 2026
Application No. 18/781,059

SEMICONDUCTOR DEVICE AND METHOD

Non-Final OA §102§103
Filed
Jul 23, 2024
Priority
Mar 29, 2022 — divisional of 12/408,420
Examiner
TRAN, TAN N
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
964 granted / 1111 resolved
+26.8% vs TC avg
Moderate +10% lift
Without
With
+10.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
31 currently pending
Career history
1153
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
50.4%
+10.4% vs TC avg
§102
33.7%
-6.3% vs TC avg
§112
7.7%
-32.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1111 resolved cases

Office Action

§102 §103
DETAILED ACTION Specification 1. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Objections 2. Claim 1 is objected to because of the following informalities: In claim 1, line 7, “the gate source region” should be changed to “the epitaxial source region” because “the gate source region” lacks of antecedent basis. Appropriate correction is required. Claim Rejections - 35 USC § 102 3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 4. Claim(s) 1 – 7, 16 - 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (10177151). With regard to claim 1, Wang et al. disclose a semiconductor device (for example, see fig. 18), comprising: a fin (referred to as “A” by examiner’s annotation shown in fig. 18 below) over a semiconductor substrate (101); an epitaxial source region (referred to as “1303A” by examiner’s annotation shown in fig. 18 below; for example, see column 7, lines 50 - 54) and an epitaxial drain region (referred to as “1303B” by examiner’s annotation shown in fig. 18 below; for example, see column 7, lines 50 - 54) in the fin (A); a gate structure (referred to as “GT” by examiner’s annotation shown in fig. 18 below) extending over the fin (A) between the epitaxial source region (1303A) and the epitaxial drain region (1303B), the gate structure (GT) comprising a gate electrode material (referred to as “1616A” by examiner’s annotation shown in fig. 18 below) over a gate dielectric material (referred to as “GD” by examiner’s annotation shown in fig. 18 below; or see column 8, lines 36 – 42 discloses a gate electrode formed on a gate dielectric layer); a first doped region (referred to as “D” by examiner’s annotation shown in fig. 18 below; wherein the doped region D including P-Well and N-Well regions) of the fin (A) adjacent the epitaxial source region (1303A) opposite the gate structure (GT), wherein the epitaxial source region (1303A) extends into the first doped region (D); a control structure (referred to as “CT” by examiner’s annotation shown in fig. 18 below; wherein this transistor acts as the active control structure within a larger control circuit. By using a tiny input signal at one terminal to regulate a much larger power flow through its other terminals. It functions as electronic switch or an analog signal controller. Although the applicant uses terms different to those of Wang et al. to label/describe the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. The use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements.) extending over the first doped region (D), the control structure (CT) comprising the gate electrode material (1616A) over the gate dielectric material (referred to as “GD” by examiner’s annotation shown in fig. 18 below; or see column 8, lines 36 – 42 discloses a gate electrode formed on a gate dielectric layer); and an epitaxial resistor region (referred to as “1303C” by examiner’s annotation shown in fig. 18 below; wherein the epitaxial region 1303C, having a resistance, functions as an epitaxial resistor region) in the fin (A), wherein the epitaxial resistor region (1303C) extends into the first doped region (D). PNG media_image1.png 773 961 media_image1.png Greyscale With regard to claim 2, Wang et al. disclose a semiconductor device (for example, see fig. 18), comprising: a fin (referred to as “A” by examiner’s annotation shown in fig. 18 below) over a semiconductor substrate (101); an epitaxial source region (referred to as “1303A” by examiner’s annotation shown in fig. 18 below; for example, see column 7, lines 50 - 54) and an epitaxial drain region (referred to as “1303B” by examiner’s annotation shown in fig. 18 below; for example, see column 7, lines 50 - 54) in the fin (A); a gate structure (referred to as “GT” by examiner’s annotation shown in fig. 18 below) extending over the fin (A) between the epitaxial source region (1303A) and the epitaxial drain region (1303B), the gate structure (GT) comprising a gate electrode material (referred to as “1616A” by examiner’s annotation shown in fig. 18 below) over a gate dielectric material (referred to as “GD” by examiner’s annotation shown in fig. 18 below; or see column 8, lines 36 – 42 discloses a gate electrode formed on a gate dielectric layer); a first doped region (referred to as “D” by examiner’s annotation shown in fig. 18 below; wherein the doped region D including P-Well and N-Well regions) of the fin (A) adjacent the epitaxial source region (1303A) opposite the gate structure (GT), wherein the epitaxial source region (1303A) extends into the first doped region (D); a control structure (referred to as “CT” by examiner’s annotation shown in fig. 18 below; wherein this transistor acts as the active control structure within a larger control circuit. By using a tiny input signal at one terminal to regulate a much larger power flow through its other terminals. It functions as electronic switch or an analog signal controller. Although the applicant uses terms different to those of Wang et al. to label/describe the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. The use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements.) extending over the first doped region (D), the control structure (CT) comprising the gate electrode material (1616A) over the gate dielectric material (referred to as “GD” by examiner’s annotation shown in fig. 18 below; or see column 8, lines 36 – 42 discloses a gate electrode formed on a gate dielectric layer); and an epitaxial resistor region (referred to as “1303C” by examiner’s annotation shown in fig. 18 below; wherein the epitaxial region 1303C, having regions 1303, 1808 with a resistance, functions as an epitaxial resistor region) in the fin (A), wherein the epitaxial resistor region (1303C) extends into the first doped region (D); wherein the epitaxial resistor region (1303C) is free of contacts. PNG media_image2.png 618 782 media_image2.png Greyscale With regard to claim 3, Wang et al. disclose a contact (a contact 1616 or a contact 1808) on (on a top or on a sidewall) the control structure (CT). With regard to claim 4, Wang et al. disclose the first doped region (D) comprises N-well region having n-type and the epitaxial source region (1303A) is n-type. With regard to claim 5, Wang et al. disclose a second doped region (a top region of PW region functions as a second doped region) of the fin (A), wherein the gate structure (GT) extends over the second doped region (the top region of PW region functions as the second doped region). With regard to claim 6, Wang et al. disclose the epitaxial source region (1303A) extends into the second doped region (the top region of PW region functions as the second doped region). With regard to claim 7, Wang et al. disclose a distance between the epitaxial source region (1303A) and the epitaxial resistor region (1303C) is greater than a distance between the epitaxial source region (1303A) and the epitaxial drain region (1303B). With regard to claim 16, Wang et al. disclose a device (for example, see fig. 18), comprising: a semiconductor fin (referred to as “A” by examiner’s annotation shown in fig. 18 below) protruding from a substrate (101); an n-type channel region (referred to as “1218A” by examiner’s annotation shown in fig. 18 below; wherein the channel region 1218A, formed between the N-type source/drain regions 1303, functions as n-type channel region) in the fin (A); a p-type channel region (referred to as “1218B” by examiner’s annotation shown in fig. 18 below; wherein the channel region 1218B, formed between the P-type source/drain regions 1303, functions as p-type channel region) in the fin (A), wherein the p-type channel region (1218A) is adjacent the n-type channel region (1218B); first gate structure (referred to as “G1” by examiner’s annotation shown in fig. 18 below) over the n-type channel region (1218A) and a second gate structure (referred to as “G2” by examiner’s annotation shown in fig. 18 below) over the p-type channel region (1218B); a first epitaxial region (referred to as “1303A” by examiner’s annotation shown in fig. 18 below) in the fin (A) adjacent a first side of the first gate structure (G1); a second epitaxial region (referred to as “1303B” by examiner’s annotation shown in fig. 18 below) in the fin (A) adjacent a second side of the first gate structure (G1) and adjacent a first side of the second gate structure (referred to as “G2” by examiner’s annotation shown in fig. 18 below); and a third epitaxial region (referred to as “1303C” by examiner’s annotation shown in fig. 18 below) in the fin (A) adjacent a second side of the second gate structure (G2). PNG media_image3.png 686 941 media_image3.png Greyscale With regard to claim 17, Wang et al. disclose a device (for example, see fig. 18), comprising: a semiconductor fin (referred to as “A” by examiner’s annotation shown in fig. 18 below) protruding from a substrate (101); an n-type channel region (referred to as “1218A” by examiner’s annotation shown in fig. 18 below; wherein the channel region 1218A, formed between the N-type source/drain regions 1303, functions as n-type channel region) in the fin (A); a p-type channel region (referred to as “1218B” by examiner’s annotation shown in fig. 18 below; wherein the channel region 1218B, formed between the P-type source/drain regions 1303, functions as p-type channel region) in the fin (A), wherein the p-type channel region (1218A) is adjacent the n-type channel region (1218B); first gate structure (referred to as “G1” by examiner’s annotation shown in fig. 18 below) over the n-type channel region (1218A) and a second gate structure (referred to as “G2” by examiner’s annotation shown in fig. 18 below) over the p-type channel region (1218B); a first epitaxial region (referred to as “1303A” by examiner’s annotation shown in fig. 18 below) in the fin (A) adjacent a first side of the first gate structure (G1); a second epitaxial region (referred to as “1303B” by examiner’s annotation shown in fig. 18 below) in the fin (A) adjacent a second side of the first gate structure (G1) and adjacent a first side of the second gate structure (referred to as “G2” by examiner’s annotation shown in fig. 18 below); and a third epitaxial region (referred to as “1303C” by examiner’s annotation shown in fig. 18 below) in the fin (A) adjacent a second side of the second gate structure (G2). wherein the first epitaxial region (1303A), the second epitaxial region (1303B), and the third epitaxial region (1303C) are n-type. PNG media_image4.png 666 906 media_image4.png Greyscale With regard to claim 18, Wang et al. disclose a first epitaxial contact (a contact 1808, is directly contact with the first epitaxial region 1303A, functions as a first epitaxial contact) on the first epitaxial region (1303A). With regard to claim 19, Wang et al. disclose a dummy gate structure (for example, see column 3, lines 6, 7, column 5, lines 35, 36) over the n-type channel region. With regard to claim 20, Wang et al. disclose the n-type channel region (1218A wherein the n-type channel region 1218A formed in a middle portion of the NW region) is longer than the p-type channel region (1218B wherein the p-type channel region 1218B formed in a top portion of the PW region). Claim Rejections - 35 USC § 103 5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 6. Claims 9 – 11, 13 – 15 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (10049938) in view of Rajashekhar et al. (12219776). With regard to claim 9, Wang et al. (10049938) disclose a device (for example, see fig. 18A), comprising: a semiconductor fin (129) protruding from a substrate (50); a first epitaxial region (referred to as “34A” by examiner’s annotation shown in fig. 18A below) in the semiconductor fin (129); a second epitaxial region (referred to as “34B” by examiner’s annotation shown in fig. 18A below) in the semiconductor fin (129); a first channel region (referred to as “66A” by examiner’s annotation shown in fig. 18A below) in the semiconductor fin (129), wherein the first channel region (66A) extends from the first epitaxial region (34A) to the second epitaxial region (34B); a third epitaxial region (34C) in the semiconductor fin (129); a second channel region (referred to as “66B” by examiner’s annotation shown in fig. 18A below) in the semiconductor fin (129), wherein the second channel region (66B) extends from the second epitaxial region (34B) to the third epitaxial region (34C); a first gate structure (referred to as “102A” by examiner’s annotation shown in fig. 18A below) on the first channel region (66A); and a second gate structure (referred to as “102B” by examiner’s annotation shown in fig. 18A below) on the second channel region (66B). PNG media_image5.png 585 671 media_image5.png Greyscale Wang et al. (10049938) do not clearly disclose the second channel region, the second region, and the third region have the same doping type. However, Rajashekhar et al. discloses the second channel region (45), the second region (42), and the third region (48) have the same doping type. (for example, see column 21, lines 50 – 52). PNG media_image6.png 457 627 media_image6.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Wang et al. (10049938)’s device to have the second channel region, the second region, and the third region have the same doping type as taught by Rajashekhar et al. in order to enhance an electron mobility efficiency of the channel region for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. With regard to claim 10, Wang et al. (10049938) disclose the first epitaxial region (34A) can be an epitaxial drain region and the second epitaxial region (34B) can be an epitaxial source region. With regard to claim 11, Wang et al. (10049938) disclose the second channel region (66B) made of germanium is conductive. With regard to claim 13, Wang et al. (10049938) disclose the doping type of the second channel region is p-type. (p-well is formed in the epitaxial fins 66. Therefore, there is inherently the doping type of the second channel region is p-type; for example, column 5, lines 11, 12). With regard to claim 14, Wang et al. (10049938) disclose the first epitaxial region (34A) and the second epitaxial region (34B) are separated by a first distance, and wherein the second epitaxial region (34B) and the third epitaxial region (34C) are separated by the first distance. With regard to claim 15, Wang et al. (10049938) disclose the second gate structure (102B) is a dummy gate structure. (for example, see column 12, line 67). Allowable Subject Matter 7. Claims 8, 12 would be allowable if rewritten to overcome the objection(s), set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Claims 8, 12 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as an epitaxial dummy region in the fin, wherein the epitaxial dummy region extends into the first doped region as recited in claim 8, a current path through the second channel region, the second epitaxial region, and the third epitaxial region has a resistance in the range of 150 ohms to 2000 ohms as recited in claim 12. Conclusion 8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TAN N TRAN/ Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jul 23, 2024
Application Filed
Aug 07, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
97%
With Interview (+10.0%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1111 resolved cases by this examiner. Grant probability derived from career allowance rate.

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