DETAILED ACTION
This Office Action is in response to the applicant's continuation application preliminary amendment filed January 8th, 2025. In virtue of this communication, claims 21-40 are currently presented in the instant application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 21, 33, and 36 are objected to because of the following informalities: in claim 21, at line 8, the limitation “image sensor die” should be --image sensing die--; in claim 33, line 2, remove the second instance of “between”; and in claim 36, at line 2, the limitation “image sending die” should be --image sensing die--. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 21 and 36-39 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11 and 18-20 of U.S. Patent No. 11,955,496 B2 (hereinafter 496). Although the claims at issue are not identical, they are not patentably distinct from each as outlined below.
With respect to claim 21, 496 discloses an image sensor, comprising:
an image sensing die having a front-side and a back-side opposite to the front-side (see column 16, line 8-9);
a plurality of pixel regions disposed within the image sensing die and respectively comprising a first doping component (photodiode doping column) with a first doping type interfacing a second doping component (photodiode doping layer) with a second doping type that is different than the first doping type (see column 16, line 10-17); and
a back-side deep trench isolation (BDTI) structure disposed between adjacent pixel regions and extending from the back-side of the image sensor die into the second doping component (photodiode doping layer) (see column 16, line 18-21),
wherein the BDTI structure comprises a doped liner with the second doping type lining a sidewall surface of a filling layer (dielectric fill layer) (see column 16, line 22-25), and
wherein the doped liner is formed by performing a doping process with a protective layer lining a deep trench followed by removing the protective layer prior to forming the filling layer (see column 16, line 26-29), resulting in a surface concentration of the doped liner to be smaller than 1 E19 /cm2 (see column 16, line 62-64).
With respect to claim 36, 496 discloses an image sensor, comprising:
a plurality of pixel regions disposed within an image sending die, a pixel region of the plurality of pixel regions comprising a first doping component (photodiode doping column) with a first doping type interfacing a second doping component (photodiode doping layer) with a second doping type that is different than the first doping type (see column 18, line 7-12);
a gate structure and a metallization stack disposed on a front-side of the image sensing die, wherein the metallization stack comprises a plurality of metal interconnect layers arranged within one or more inter-level dielectric layers (see column 18, line 18-22);
a logic die bonded to the image sensing die and comprising logic devices (see column 18, line 24-25); and
a back-side deep trench isolation (BDTI) structure between adjacent pixel regions and comprising a doped liner with the second doping type lining a sidewall surface of a filling layer (dielectric fill layer) (see column 18, line 26-31),
wherein the doped liner is formed under a protection layer followed by removing the protection layer prior to forming the filling layer, such that the doped liner is formed with a thickness smaller than 5 nm (see column 18, line 32-35).
With respect to claim 37, 496 discloses the image sensor of claim 36, wherein the doped liner has a conformity greater than 90% from top to bottom (see column 18, line 44-46).
With respect to claim 38, 496 discloses the image sensor of claim 36, wherein the doped liner is formed by: forming the protection layer lining a deep trench; performing a plasma doping process; removing the protection layer; and performing an annealing process, wherein the doped liner has a surface concentration smaller than 1 E19 /cm2 (see column 18, line 36-43)
With respect to claim 39, 496 discloses an integrated circuit, comprising:
an image sensing die having a plurality of pixel regions respectively comprising a first doping component (photodiode doping column) with a first doping type interfacing a second doping component (photodiode doping layer) with a second doping type that is different than the first doping type (see column 18, line 6-12);
a back-side deep trench isolation (BDTI) structure disposed between adjacent pixel regions and extending into the second doping component, wherein the BDTI structure comprises a doped liner with the second doping type and a filling layer (dielectric fill layer), the doped liner lining a sidewall surface of the filling layer (see column 18, line 26-31);
a doped isolation well with the second doping type disposed between the plurality of pixel regions and extending into the second doping component (see column 18, line 14-17);
a metallization stack arranged on a front-side and comprising a plurality of metal interconnect layers arranged within an inter-level dielectric layer (column 18, line 18-22); and
a logic die bonded to the front-side of the image sensing die, the logic die comprising logic devices (see column 18, line 24-25),
wherein the doped liner is formed under a protection layer followed by removing the protection layer prior to forming the filling layer (see column 18, line 32-34) resulting in the doped liner having a conformity greater than 90% from top to bottom (see column 18, line 44-46).
Allowable Subject Matter
Claims 22-35, and 40 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not disclose or fairly suggest:
wherein the doped liner has a conformity greater than 90% from top to bottom, as called for in claim 22;
wherein the doped liner has a thickness smaller than 5 nm, as called for in claim 23;
a doped isolation well with the second doping type disposed between the plurality of pixel regions and extending into the second doping component, as called for in claim 24 (claims 25-28 depend from claim 24);
wherein the BDTI structure further comprising a high-k dielectric liner disposed between the doped liner and the filling layer, as called for in claim 29;
a shallow trench isolation (STI) structure disposed between the plurality of pixel regions and extending into the second doping component, wherein the STI structure and the BDTI structure are vertically aligned, as called for in claim 30;
wherein the doped liner and the filling layer extend laterally along the back-side of the image sensing die, as called for in claim 31;
wherein the doped liner of the BDTI structure has a doping concentration in a range between approximately 5E17 atom/cm3 to approximately 1 E19 atom/cm3 as called for in claim 32;
a floating diffusion well disposed between the plurality of pixel regions and extending into the second doping component; and a transfer gate arranged on the front-side of the image sensing die at a position laterally between the first doping component or the second doping component and the floating diffusion well as called for in claim 33;.
a metallization stack arranged on the front-side of the image sensing die and comprising a plurality of metal interconnect layers arranged within one or more inter-level dielectric layers as called for in claim 34;
a logic die bonded to the image sensing die from the front-side of the image sensing die, wherein the logic die comprises logic devices as called for in claim 35; and
wherein the doped liner has a surface concentration smaller than 1 E19 /cm2 as called for in claim 40.
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference teaches an image sensor similar to that of the claimed invention: US 20180301502 A1, US 20190096929 A1.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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