DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/23/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Allowable Subject Matter
Claims 1-17 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
A. Re claim 1, the prior art cannot anticipate or render obvious the limitations of: a dielectric feature disposed over the first source/drain feature and extending along a sidewall of the dielectric fin, in combination with the additionally claimed features of claim 1.
In Re claims 2-10, they are allowable due to their dependence on claim 1.
B. Re claim 11, the prior art cannot anticipate or render obvious the limitations of: a dielectric feature disposed over the first source/drain feature and extending along a sidewall of the dielectric fin, in combination with the additionally claimed features of claim 11.
In Re claims 12-16, they are allowable due to their dependence on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US 2019/0148240 A1-IDS prior art, hereafter Xie) in view of Synder et al (US 2020/0295002 A1, hereafter Snyder).
Re claim 17, Xie discloses in FIGS. 3-39 a method, comprising:
receiving a workpiece (100; [0022]) that comprises:
a first fin structure (lower 103 in FIG. 3; [0023]) and a second fin structure (upper 103 in FIG. 3; [0023]) over a substrate (102 in FIG. 3; [0023]),
a gate structure (3 in FIG. 3; [0022]) over the first fin structure (lower 103) and the second fin structure (upper 103),
a first source/drain feature (left 116 under left 120 in FIG. 3; [0023] and [0028]) disposed over (above) the first fin structure (lower 103), and
a second source/drain feature (right 116 under right 120 in FIG. 3; [0023] and [0028]) disposed over (above) the second fin structure (upper 103);
selectively forming (patterning) a dielectric feature (119 in FIG. 37; [0051]) over the first source/drain feature (left 116 under left 120); and
after the selectively forming (patterning), forming a contact structure (139/170 in FIG. 37; [0051]) over the first source/drain feature (left 116 under left 120) and the second source/drain feature (right 116 under right 120) such that the contact structure (139/170) is electrically connected to (contacting) the second source/drain feature (right 116 under right 120) and is separated (isolated) from the first source/drain feature (left 116 under left 120) by the dielectric feature (119).
Xie fails to disclose the gate structure wrapping over the first fin structure and the second fin structure.
However,
Synder discloses in FIG. 1A a workpiece (101 comprising finFETS; [0001]-[0002]), comprising: a gate structure (119a; [0028]) wrapping (tri-gate; [0011]) over a first fin structure (120; [0030]) and a second fin structure (121; [0030]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Xie, by using the gate structure of Snyder, the gate structure wrapping over the first fin structure and the second fin structure, for devices with different channel widths, tailored according to current capacity, rating, other appropriate characteristics, and/or design factors associated with the transistors, rather than being dictated by a global channel width for all the non-planar transistors in the workpiece (Snyder; [0010]).
Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie and Snyder as applied to claim 17 above, and further in view of Chang et al (US 9,627,316 B1, hereafter Chang).
Re claims 18 and 20, Xie discloses the method of claim 17.
But, fails to disclose wherein the selectively forming comprises: forming a photoresist layer over the first source/drain feature (left 116 under left 120) and the second source/drain feature (right 116 under left 120); patterning the photoresist layer to form a patterned photoresist layer that includes an opening to expose the first source/drain feature (left 116 under left 120); depositing a dielectric material in the opening, and etching back the dielectric material to form the dielectric feature (119); and before the forming of the contact structure (139/170), forming a liner along sidewalls of the dielectric feature (119).
However,
Chang discloses in FIGS. 2A-2L a method comprising: forming a photoresist layer (as-deposited 172; col. 3, line 65 – col. 4, line 34) over a conductive feature (164; col. 3, lines 46-64); patterning (FIGS. 2C-2D) the photoresist layer (172) to form a patterned photoresist layer (col. 3, line 65 – col. 4, line 54) that includes an opening (173; col. 3, line 65 – col. 4, line 54) to expose the conductive feature (164); depositing a dielectric material (174 in FIG. 2E; col. 4, lines 55-65) in the opening (173), and etching back (FIG. 2F; col. 5, lines 7-16) the dielectric material (174) to form a dielectric feature (174a; col. 5, lines 7-16); and before the forming of a contact structure (180a; col. 6, lines 3-13), forming a liner (176a in FIG. 2I; col. 5, lines 43-60) along sidewalls (174b; col. 5, lines 22-42) of the dielectric feature (174a).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Xie, by using the methods of Chang to form a photoresist layer over the first source/drain feature (left 116 under left 120) and the second source/drain feature (right 116 under left 120); pattern the photoresist layer to form a patterned photoresist layer that includes an opening to expose the first source/drain feature (left 116 under left 120); deposit a dielectric material in the opening, and etching back the dielectric material to form the dielectric feature (119); and before the forming of the contact structure (139/170), form a liner along sidewalls of the dielectric feature (119), to decrease the size or dimension of the contact structure without compromising the reliability of the contact structure. Thus, the contact structure and the finFET device having the contact structure therein in accordance with the above embodiments of the present disclosure offers lower contact resistance, improved reliability and better performance (Chang; col. 6, line 60 – col. 7, line 2).
Claims 19 is rejected under 35 U.S.C. 103 as being unpatentable over Xie and Snyder and Chang as applied to claim 18 above, and further in view of Standaert al (US 2008/0026568 A1, hereafter Standaert).
Re claim 19, Xie and Snyder and Chang disclose the method of claim 18.
But, fail to disclose wherein the etching back removes the patterned photoresist layer (172 of Chang).
However,
Standaert discloses in FIGS. 6-11 a method comprising: an etching process (FIG. 9) comprising selective ([0033]) and non-selective etching ([0033]) of a dielectric material (IPL 52; [0031]) and a conductive material (50; [0033]), and concurrent etching back (wet-etching; [0033]) of the dielectric material (IPL 52) and a patterned photoresist layer (photo-mask 54; [0032]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Xie and Snyder and Chang, by using the concurrent etching back of Standaert, such that the etching back removes the patterned photoresist layer (172 of Chang), for selective formation of the dielectric feature (Standaert; [0032]-[0033]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
11264393-B2; and US-6083828-A discloses dielectric features over source/drain regions without the specificity required for claims 1; 11; and 17, for a first source/drain feature disposed over the first fin structure and a second source/drain feature disposed over the second fin structure, a dielectric feature disposed over the first source/drain feature, and a contact structure formed over the first source/drain feature and the second source/drain feature. The contact structure is electrically coupled to the second source/drain feature and is separated from the first source/drain feature by the dielectric feature, reducing the number of metal lines while maintaining the same connectivity using elongated source/drain contacts that spans over more than one active region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408)918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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