DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 24, 27-30, 31, 35-37 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 24/27/29/31/35 recites the limitation "the computation module". There is insufficient antecedent basis for this limitation in the claim.
Claim 28 is rejected at least because it is a dependent claim of claim 27.
Claim 30 is rejected at least because it is a dependent claim of claim 29.
Claim 36-37 is rejected at least because it is a dependent claim of claim 35.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-22, 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kitagawa et al. (Patent 8482950), hereinafter as Kitagawa.
Regarding claim 21, Kitagawa teaches a computing device, comprising:
a memory array comprising a plurality of memory cells grouped in rows and columns of memory cells, each of the memory cells comprising a memory unit adapted to store data, and a read port having a read-enable input and an output (Fig 4, each cell has a WL as read-enable input, and outputted to a BL);
a plurality of read-enable lines, each connected to, and adapted to transmit an input signal to, the read-enable inputs of the read ports of a respective row of memory cells (Fig 4, word lines as read-enable lines, each WL for a row);
a plurality of data-output lines, each connected to the outputs of the read ports of a respective column of memory cells (Fig 4, BLs);
an output interface comprising an analog-to-digital converter (ADC) having a plurality of analog inputs, each with a respective input capacitor; and
a plurality of switching devices adapted to (Fig 9, CSL 51 for each BL and selection gates 171s): connect the data-output lines to respective non-overlapping plurality of subsets of the input capacitors, each of the plurality of subsets having a respective total capacitance, at least two of the plurality of subsets of input capacitors having different total capacitance from each other, and connect the plurality of subsets of capacitors to each other in parallel (it is obvious the different combination of Csel<0-3> for different selected BL can have different capacitance (with parallelly connected 171s)); except capacitors are arranged non-overlapping, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have each BL has the same arrangement as in Fig 9, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 22, Kitagawa teaches an input interface connected to the plurality of read-enable lines and configured to generate a plurality of pulses on each of at least subset of the plurality of read-enable lines (Fig 4, row decoder and wl driver).
Regarding claim 25, Kitagawa teaches a digital read/write (RW) interface connected to the memory array and adapted to read and write data from and to the memory cells (Fig 4).
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kitagawa, in view of Hecht (PGPUB 20190228825), hereinafter as Hecht.
Regarding claim 26, Kitagawa teaches a device as rejection of claim 21,
But expressly the memory cell is a SRAM cell,
Hecht teaches each of the memory cells is an eight- transistor static random-access memory (SRAM) cell having a six-transistor SRAM memory unit having two inverters reverse-coupled to each other and two access transistors, each switchably connecting a respective junction between the two invertors to a respective data line through which data to be written to the six-transistor SRAM memory unit is transmitted, the read port having a first and second transistors, each having a control electrode and a main current path, the control electrode being adapted to control current flow through the current path the main paths being serially connected between the data-output line and a voltage reference point, the control electrode of one of the first transistor being connected to the read-enable line for the memory cell, and the control electrode of one of the first transistor being connected to a junction between the two inverters (Fig 4, SRAM cell matches the circuit above).
Since Hecht and Kitagawa are both from the same field of memory device, the purpose disclosed by Hecht would have been recognized in the pertinent art of Kitagawa.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use six transistor SRAM as in Hecht into the device of Kitagwa for the purpose of enabling a memory device.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 11322195 or claim 1-20 of patent 12073869. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant app
11322195(‘5)/12073869(‘9)
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720
1112
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Or
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612
916
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‘5:
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640
394
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582
392
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Claim 21/32
‘9
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314
386
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544
392
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222
402
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Claim 22,
‘5: claim 8
23/34
‘5: claim 9
24/35
‘5: claim 1
25
‘5: claim 4
26/40
‘5: claim 5
27/28/37/38
‘5: claim 7
29/30
‘5: claim 12
31/36
‘5: claim 6
33/39
‘5: claim 7, 10
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MIN HUANG/Primary Examiner, Art Unit 2827