DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6, 9-10, and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su et al. (U.S. Patent No. 9,136,206).
Regarding to claim 1, Su teaches a semiconductor structure comprising:
a substrate including a transistor (Fig. 11, element 20);
a dielectric layer disposed on the substrate (Fig. 11, element 24);
a first conductive feature formed in the dielectric layer to be spaced apart from the transistor by the dielectric layer (Fig. 11, element 42; column 3, lines 7-8); and
a second conductive feature penetrating the first conductive feature and the dielectric layer, and being electrically connected to the first conductive feature and the transistor (Fig. 11, element 56A/B; column 4, lines 10-14).
Regarding to claim 2, Su teaches the first conductive feature and the second conductive feature are made of different materials (column 3, lines 7-8, first conductive feature 42 contain aluminum; column 4, lines 10-14, second conductive feature 56B comprises copper).
Regarding to claim 3, Su teaches
the first conductive feature is made of a material including copper, ruthenium, tungsten, titanium, aluminum, cobalt, molybdenum, iridium, rhodium, graphene or combinations thereof (column 3, lines 7-8, aluminum), and
the second conductive feature is made of a material including copper, ruthenium, tungsten, titanium, aluminum, cobalt, molybdenum, iridium, rhodium, cobalt-tungsten-phosphorus or combinations thereof (column 4, lines 10-14, copper).
Regarding to claim 6, Su teaches the second conductive feature has an outer wall that forms an included angle with the transistor, the included angle ranging from 72 degrees to 90 degrees (Fig. 11, 90 degrees).
Regarding to claim 9, Su teaches a semiconductor structure comprising:
a substrate including a transistor (Fig. 11, element 20);
a first dielectric layer disposed on the substrate (Fig. 11, element 24);
an interconnect structure including
a first conductive feature that is disposed on the first dielectric layer opposite to the substrate, the first conductive feature being spaced apart from the transistor (Fig. 11, element 42; column 3, lines 7-8), and
a second dielectric layer that surrounds the first conductive feature (Fig. 11, element 36; column 2, line 46); and
a second conductive feature penetrating the interconnect structure and being electrically connected to the first conductive feature and the transistor (Fig. 11, element 56B; column 4, lines 10-14).
Regarding to claim 10, Su teaches
a glue layer that is disposed between the first dielectric layer and the first conductive feature and that extends in a direction substantially parallel to the substrate (Fig. 11, element 38); and
a liner/barrier layer that is connected to and surrounds the second conductive feature (Fig. 11, element 56A).
Regarding to claim 16, Su teaches the second conductive feature is electrically connected to multiple contacts of the transistor (Fig. 11).
Regarding to claim 17, Su teaches a semiconductor structure comprising:
a substrate including a transistor (Fig. 11, element 20);
contact structures that are respectively connected to source/drain regions of the transistor, and that are respectively disposed at two opposite sides of a gate structure of the transistor (Fig. 11, elements 50);
a first dielectric layer that covers the gate structure (Fig. 11, element 36);
a second dielectric layer having multiple portions that cover the contact structures, respectively (Fig. 11, element 52);
a third dielectric layer disposed over the first dielectric layer and the second dielectric layer (Fig. 11, element 54);
a first conductive feature that is disposed on the third dielectric layer opposite to the substrate, and that includes multiple conductive components (Fig. 11, element including conductive components 38/40/42);
a fourth dielectric layer disposed on the third dielectric layer and around the multiple conductive components (Fig. 11, element 60); and
a second conductive feature penetrating one of the multiple conductive components and penetrating the third dielectric layer and the second dielectric layer so as to permit the one of the multiple conductive components to be brought into electrical connection with one of the contact structures through the second conductive feature (Fig. 11, element 56B, second conductive feature 56 penetrating conductive component 42 and penetrating the third dielectric layer 54 and the second dielectric layer 52 to permit the multiple conductive component 42 to be brought into electrical connection with the contact structures through the second conductive feature 56. Note that in a circuit, all structures are electrical connected with each other depend on switching status.).
Regarding to claim 18, Su teaches a material of the first dielectric layer is different from a material of the second dielectric layer, and a material of the third dielectric layer is different from each of the material of the first dielectric layer and the material of the second dielectric layer (Fig. 11, the first dielectric layer 36 is the gate dielectric formed of high k-dielectric material, the second dielectric layer 52 is etch stop layer formed on silicon nitride, the third dielectric layer 54 formed of PSG, BSG, BPSG, or TEOS oxide).
Regarding to claim 19, Su teaches liner/barrier layer that is disposed around the second conductive feature (Fig. 11, element 56A).
Regarding to claim 20, Su teaches the liner/barrier layer is disposed to prevent the second conductive feature from being in contact with the first conductive feature (Fig. 11, the barrier layer 56A is disposed to prevent the second conductive feature 56B from being in contact with the first conductive feature 42).
Claims 1-2, 6, 9-10, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kamineni et al. (U.S. Patent No. 9,679,807).
Regarding to claim 1, Kamineni teaches a semiconductor structure comprising:
a substrate including a transistor (Fig. 3E, element 310);
a dielectric layer disposed on the substrate (Fig. 3E, dielectric layer including layer 346 and layer 348);
a first conductive feature formed in the dielectric layer to be spaced apart from the transistor by the dielectric layer (Fig. 3E, element 342, column 6, line 7); and
a second conductive feature penetrating the first conductive feature and the dielectric layer, and being electrically connected to the first conductive feature and the transistor (Fig. 3E, element 360; column 6, lines 30-31).
Regarding to claim 2, Kamineni teaches the first conductive feature and the second conductive feature are made of different materials (Fig. 3E).
Regarding to claim 6, Kamineni teaches the second conductive feature has an outer wall that forms an included angle with the transistor, the included angle ranging from 72 degrees to 90 degrees (Fig. 3E).
Regarding to claim 9, Kamineni teaches a semiconductor structure comprising:
a substrate including a transistor (Fig. 3E, element 310);
a first dielectric layer disposed on the substrate (Fig. 3E, dielectric layer including layer 346 and layer 348);
an interconnect structure including
a first conductive feature that is disposed on the first dielectric layer opposite to the substrate, the first conductive feature being spaced apart from the transistor (Fig. 3E, element 342), and
a second dielectric layer that surrounds the first conductive feature (element 320); and
a second conductive feature penetrating the interconnect structure and being electrically connected to the first conductive feature and the transistor (element 360).
Regarding to claim 10, Kamineni teaches
a glue layer that is disposed between the first dielectric layer and the first conductive feature and that extends in a direction substantially parallel to the substrate (Fig. 3E, element 344); and
a liner/barrier layer that is connected to and surrounds the second conductive feature (Fig. 3E, element 364).
Regarding to claim 16, Kamineni teaches the second conductive feature is electrically connected to multiple contacts of the transistor (Fig. 3E).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (U.S. Patent No. 9,136,206), as applied to claim 1 above, and further in view of Chan et al. (U.S. Patent No. 10,741,493).
Regarding to claim 4, Su teaches a liner layer that surrounds and that is connected to the second conductive feature (Fig. 11, element 56A) and the second conductive feature being connected to the first conductive feature through and the barrier layer (Fig. 11).
Su does not disclose a barrier layer that surrounds and that is connected to the liner layer, the second conductive feature being connected to the first conductive feature through the liner layer and the barrier layer.
Chan discloses a barrier layer that surrounds and that is connected to the liner layer, the second conductive feature being connected to the first conductive feature through the liner layer and the barrier layer (Fig. 11, barrier layer 260 surrounds and connected to the liner layer 270, the second conductive feature 234 being connected to the first conductive feature 210 through the liner layer 270 and the barrier layer 260). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Su in view of Chan to configure a barrier layer that surrounds and that is connected to the liner layer, the second conductive feature being connected to the first conductive feature through the liner layer and the barrier layer, in order to increase adhesion and prevent diffusion.
Regarding to claim 5, Su as modified discloses each of the barrier layer and the liner layer is made of a conductive material including tantalum, tantalum nitride, cobalt, ruthenium, titanium, titanium nitride, manganese nitride, or combinations thereof (Su, column 4, lines 10-11; Chan, column 7, lines 62-65).
Allowable Subject Matter
Claims 7-8 and 11-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 7, the prior art fails to anticipate or render obvious the claimed limitations including “the dielectric layer is formed with an air gap adjacent to the first conductive feature” in combination with the limitations recited in claim 1.
Regarding to claim 8, the prior art fails to anticipate or render obvious the claimed limitations including “the second conductive feature penetrates through the lower surface and the upper surface of the first conductive feature” in combination with the limitations recited in claim 1 and the rest of limitations recited in claim 8.
Regarding to claim 11, the prior art fails to anticipate or render obvious the claimed limitations including “the first conductive feature includes multiple conductive components that are separated from each other by multiple portions of the second dielectric layer” in combination with the limitations recited in claim 9.
Regarding to claim 14, the prior art fails to anticipate or render obvious the claimed limitations including “a bottom surface of the second conductive feature is connected to a contact of the transistor and is lower than the bottom surface of the first conductive feature” in combination with the limitations recited in claim 9 and the rest of limitations recited in claim 14.
Claim 17 would be allowable if amended to include the limitations of claim 7, 8, 11, or 14.
Pertinent Art
For the benefits of the Applicant, US-10032712-B2, US-10290536-B2, US-9437540-B2, US-20190363048-A1, US-7834457-B2, US-6444544-B1, US-7803704-B2, US-8835319-B2, US-9397045-B2, and US-20040251552-A1, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references fail to disclose “a second conductive feature penetrating one of the multiple conductive components and penetrating the third dielectric layer and the second dielectric layer so as to permit the one of the multiple conductive components to be brought into electrical connection with one of the contact structures through the second conductive feature.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM.
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/VU A VU/Primary Examiner, Art Unit 2897
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