DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
IDS
The IDS document(s) filed on 07/23/2024 and 12/11/2024 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-9, 11 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2004/0232552 A1), hereafter “Wang”.
As to claim 1, Wang teaches a semiconductor structure, comprising:
a substrate (12, Fig. 9, ⁋ [0032]) with a conductive structure (10, ⁋ [0032]) thereon;
a conductive layer (22, ⁋ [0037]) disposed on the substrate, and including a first conductive feature (middle 22 of Fig. 9), the first conductive feature being electrically connected to the conductive structure (⁋ [0007]);
an interconnect (40+42, ⁋ [0043]) electrically connected to the first conductive feature (⁋ [0007]);
a first dielectric layer (26, ⁋ [0039]) adjoining the first conductive feature;
a second dielectric layer (32, ⁋⁋ [0041]-[0044]) disposed on the first dielectric layer and adjoining the interconnect; and
an etch stop layer (30, ⁋⁋ [0041], [0007]) disposed between the first dielectric layer (26) and the second dielectric layer (32) and surrounding a portion of the interconnect (40+42), a bottom surface of the etch stop layer being spaced apart from an upper surface of the first conductive feature (middle 22) in a vertical direction (Fig. 9).
As to claim 2, Wang teaches the semiconductor structure according to claim 1, wherein a top surface of the first dielectric layer (26) is located at a level higher than a level of the upper surface of the first conductive feature (middle 22) (Fig. 9).
As to claim 3, Wang teaches the semiconductor structure according to claim 1, wherein an air gap (28, ⁋ [0040]) is formed in the first dielectric layer (26).
As to claim 4, Wang teaches the semiconductor structure according to claim 1, wherein the interconnect (40+42) has an upper portion that is located above the etch stop layer (30), a middle portion that is surrounded by the etch stop layer, and a bottom portion that is located below the etch stop layer and in contact with the first conductive feature (Fig. 9 shows the recited limitations).
As to claim 6, Wang teaches the semiconductor structure according to claim 1, wherein the first dielectric layer (26) surrounds the first conductive feature (middle 22) so as to isolate the first conductive feature from a second conductive feature (right 22) of the conductive layer (Fig. 9).
As to claim 7, Wang teaches the semiconductor structure according to claim 6, wherein the upper surface of the first conductive feature (middle 22) is flush with an upper surface of the second conductive feature (right 22).
As to claim 8, Wang teaches the semiconductor structure according to claim 7, wherein a top surface of the first dielectric layer (26) is at a level higher than a level of each of the upper surface of the first conductive feature (middle 22) and the upper surface of the second conductive feature (right 22) (Fig. 9).
As to claim 9, Wang teaches the semiconductor structure according to claim 6, wherein the etch stop layer (30) is disposed to prevent from being in contact with the first conductive (middle 22) feature and the second conductive feature (right 22) (Fig. 9).
As to claim 11, Wang teaches a semiconductor structure, comprising:
a substrate (12, Fig. 9, ⁋ [0032]) with a conductive structure (10, ⁋ [0032]) thereon;
a conductive layer (22, ⁋ [0037]) disposed on the substrate, and including a first conductive feature (middle 22 of Fig. 9) and a second conductive feature (right 22 of Fig. 9), the first conductive feature being electrically connected to the conductive structure (⁋ [0007]);
an interconnect (40+42, ⁋ [0043]) electrically connected to the first conductive feature (⁋ [0007]);
a first dielectric layer (26, ⁋ [0039]) isolating the first conductive feature and the second conductive feature;
a second dielectric layer (32, ⁋⁋ [0041]-[0044]) disposed on the first dielectric layer and adjoining the interconnect; and
an etch stop layer (30, ⁋⁋ [0041], [0007]) disposed between the first dielectric layer and the second dielectric layer,
the interconnect having an upper portion that is located above the etch stop layer, a middle portion that is surrounded by the etch stop layer, and a bottom portion that is located below the etch stop layer and in contact with the first conductive feature, the etch stop layer being located at a level above a level of a bottom surface of the bottom portion (Fig. 9 shows the recited limitations).
As to claim 16, Wang teaches the semiconductor structure according to claim 11, wherein the first dielectric layer (26) has a vertical portion disposed between the first conductive feature (middle 22) and the second conductive feature (right 22), and a horizontal portion disposed between the second conductive feature and the second dielectric layer (32) (Fig. 9).
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5 and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, and further in view of Lu et al. (US 2017/0053863 A1), hereafter “Lu”.
As to claim 5, Wang teaches the semiconductor structure according to claim 4, but fails to teach wherein the upper portion of the interconnect has a width that is larger than a width of each of the middle portion and the bottom portion.
Lu teaches a similar device with an interconnection (280, Fig. 10, ⁋ [0037]) with an upper portion, middle portion surrounded by an etch stop layer (235, ⁋ [0025]), and bottom portion wherein the upper portion has a width larger than a width of the middle portion and bottom portion.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the interconnection structure’s width as taught by Lu into the device of Wang as it would have been an obvious matter of design choice bounded by well known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions.
As to claim 12, Wang teaches the semiconductor structure according to claim 11, but fails to teach wherein the middle portion of the interconnect has a width that is smaller than a width of each of the upper portion and the bottom portion.
Lu teaches a similar device with an interconnection (280, Fig. 10, ⁋ [0037]) with an upper portion, middle portion surrounded by an etch stop layer (235, ⁋ [0025]), and bottom portion wherein the middle portion has a width smaller than a width of the upper portion and bottom portion.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the interconnection structure’s width as taught by Lu into the device of Wang as it would have been an obvious matter of design choice bounded by well known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions.
As to claim 13, Wang teaches the semiconductor structure according to claim 11, but fails to teach wherein the etch stop layer has a first sub-layer that is formed on a top surface of the first dielectric layer, and a second sub-layer that is formed between the first dielectric layer and the middle portion of the interconnect.
Lu teaches a similar device with an interconnection (280, Fig. 10, ⁋ [0037]) with an upper portion, middle portion surrounded by an etch stop layer (235, ⁋ [0025]), and bottom portion wherein the etch stop layer has a first sub-layer formed on top of a dielectric layer (220, ⁋ [0018]) and second sub-layer (⁋ [0025], “dip portion”) that is formed between the dielectric layer and middle portion of the interconnect.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the interconnection structure’s width as taught by Lu into the device of Wang due to the dip portion being beneficial in the alignment process of forming the interconnect structure (⁋⁋ [0024]-[0025]).
As to claim 14, Wang in view of Lu teaches the semiconductor structure according to claim 13, Lu further teaches wherein the middle portion of the interconnect is surrounded by the second sub-layer (dip portion) of the etch stop layer (235) (Fig. 10).
As to claim 15, Wang in view of Lu teaches the semiconductor structure according to claim 13, Lu further teaches wherein the second sub-layer (dip portion) of the etch stop layer (235) is located above a periphery part of the bottom portion of the interconnect (Fig. 10).
Claims 10 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, and further in view of Yeh et al. (US 2018/0233406 A1), hereafter “Yeh”.
As to claim 10, Wang teaches the semiconductor structure according to claim 6, but fails to teach further comprising a patterned mask that covers an upper surface of the second conductive feature without covering the upper surface of the first conductive feature.
Yeh teaches a similar device wherein the patterned mask layer (320, Fig. 4, ⁋⁋ [0017], [0019]) is disposed between a dielectric layer (710, ⁋ [0022], Fig. 8) and conductive layer (310, Fig. 3, ⁋ [0016]) and only covers an upper surface of the outer conductive layers without covering an inner conductive feature.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the hard mask pattern as taught by Yeh into the device of Wang for the purpose of protecting a portion of the conductive layer during an etching process (⁋ [0017]).
As to claim 17, Wang teaches a semiconductor structure, comprising:
a substrate (12, Fig. 9, ⁋ [0032]) with a conductive structure thereon;
a conductive layer (22, ⁋ [0037]) disposed on the substrate, and including a first conductive feature (middle 22 of Fig. 9) and a second conductive feature (right 22 of Fig. 9), the first conductive feature being electrically connected to the conductive structure (⁋ [0007]);
an interconnect (40+42, ⁋ [0043]) electrically connected to the first conductive feature (⁋ [0007]);
a first dielectric layer (26, ⁋ [0039]) adjoining the first conductive feature and separating the first conductive feature and the second conductive feature;
a second dielectric layer (32, ⁋⁋ [0041]-[0044]) disposed on the first dielectric layer and adjoining the interconnect; and
an etch stop layer (30, ⁋⁋ [0041], [0007]) disposed between the first dielectric layer and the second dielectric layer and surrounding a portion of the interconnect.
Wang fails to teach a patterned mask layer disposed between the second dielectric layer and the conductive layer in a manner that the patterned mask layer covers an upper surface of the second conductive feature without covering an upper surface of the first conductive feature.
Yeh teaches a similar device wherein the patterned mask layer (320, Fig. 4, ⁋⁋ [0017], [0019]) is disposed between a dielectric layer (710, ⁋ [0022], Fig. 8) and conductive layer (310, Fig. 3, ⁋ [0016]) and only covers an upper surface of the outer conductive layers without covering an inner conductive feature.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the hard mask pattern as taught by Yeh into the device of Wang for the purpose of protecting a portion of the conductive layer during an etching process (⁋ [0017]).
As to claim 18, Wang modified by Yeh teaches the semiconductor structure according to claim 17, wherein the etch stop layer (30) is in contact with a top surface of the first dielectric layer (26) without being in contact with the upper surface of the first conductive feature (middle 22) (Fig. 9).
As to claim 19, Wang modified by Yeh teaches the semiconductor structure according to claim 17, Yeh further teaches wherein the etch stop layer is prevented from being formed between the second dielectric layer and the second conductive feature. Examiner notes Yeh teaches the conductive features 310 overlapped with the patterned mask layer 320 and dielectric layer 710 (see claim 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Yeh’s structure without the etch stop layer (Fig. 8) to the previously modified device of Wang into the Yeh for the purpose of forming a metal feature which provides electrical connections among various device components in a same layer of the device (⁋ [0021]).
As to claim 20, Wang modified by Yeah teach the semiconductor structure according to claim 17, wherein the upper surface of the first conductive feature (middle 22) is flush with the upper surface of the second conductive feature (right 22).
Conclusion
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/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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