DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed July 16, 2026 is acknowledged. Claims 1, 7, 10, 14-16 and 18-19 have been amended Claims 1-20 are pending.
Action on merits of claims 1-20 follows.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 12, 2026 was filed after the mailing date of the Office Action on April 20, 2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 20 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There does not appear to be a written description of the claim limitation “the method of claim 18, the first conductive layer, the second conductive layer, and the single layer of the polycrystalline material, are formed by the same formation method, wherein the first electrode, the second electrode, and the third electrode are formed to have the same thickness” (claim 20) (emphasis added) in the application as filed.
However, according to claim 18, the second conductive layer is formed by converting the first conductive layer utilizing a plasma process, thus, not “formed by the same formation method” as that of the first and third conductive layers.
Therefore, claim 20 contain new matter.
Applicant must cancel the un-support new matters in response to the Office Action.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites: “the method of claim 18, the first conductive layer, the second conductive layer, and the single layer of the polycrystalline material, are formed by the same formation method, wherein the first electrode, the second electrode, and the third electrode are formed to have the same thickness” (claim 20) (emphasis added) in the application as filed.
However, according to claim 18, the second conductive layer is formed by converting the first conductive layer utilizing a plasma process, thus, not “formed by the same formation method” as that of the first and third conductive layers.
Thus, claim 20 contravenes claim 18.
Therefore, claim 20 is indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over LIN et al. (US. Pub. No. 2021/0074805) in view of SATO et al. (US. Pub. No. 2004/0222493) all of record.
With respect to claim 1, LIN teaches a method of forming a semiconductor device, substantially as claimed, the method comprising:
forming a transistor (308) over a substrate;
forming an interconnect structure (310/312) over the transistor and the substrate;
forming an etch stop layer (106) over the interconnect structure;
forming a first conductive layer (204a) over an etch stop layer (106), wherein the first conductive layer (204a) is a polycrystalline material;
performing a treatment process to treat an upper portion of the first conductive layer (204a), wherein the treatment process converts the upper portion of the first conductive layer (204a) into a layer of an amorphous material (206); and
forming a second conductive layer (204b) over the first conductive layer (204a), wherein the second conductive layer (204b) is the polycrystalline material, wherein the first conductive layer (204a) and the second conductive layer (204b) are formed to have a same thickness using a same deposition method;
patterning the first multi-layered structure to form a first electrode (202);
forming a first dielectric layer (208) over the first electrode (202);
forming a second multi-layered structure over the first dielectric layer (208), the second multi-layered structure having the same layered structure as the first multi-layered structure (202); and
patterning the second multi-layered structure to form a second electrode (108). (See FIGs. 2A-C, 7).
Thus, LIN is shown to teach all the features of the claim with the exception of explicitly disclosing the treatment process to treat the upper portion of the first conductive layer utilizing a plasma process.
However, SATO teaches a method of forming a semiconductor device including:
forming a first multi-layered structure over an etch stop layer (11), comprising:
forming a first conductive layer (12) over the etch stop layer, wherein the first conductive layer (12) is a polycrystalline material;
performing a plasma process to treat an upper portion of the first conductive layer (12), wherein the plasma process converts the upper portion of the first conductive layer (12) into a layer of an amorphous material (33); and
forming a second conductive layer (37) over the layer (33) of the amorphous material, wherein the second conductive layer (37) is the polycrystalline material; and
patterning the first multi-layer structure to form the first electrode. (See FIGs. 16A-17F).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to perform the process to treat the upper surface portion of the first conductive layer of LIN utilizing the plasma process to treat the upper portion of the first conductive layer to convert the upper portion of the first conductive layer into the layer of an amorphous material as taught by SATO to prevent diffusion of species into the capacitor dielectric layer.
With respect to claim 11, in view of SATO, the plasma process is performed using nitrogen gas.
Claims 2-10 are rejected under 35 U.S.C. 103 as being unpatentable over LIN ‘805 and SATO ‘493 as applied to claim 1 above, and further in view of CHANG (US. Patent No. 10,290,701) of record.
With respect to claim 2, LIN, in view of SATO, teaches the method as described in claim 1 above including: forming a second dielectric layer over the second electrode.
Thus, LIN and SATO are shown to teach all the features of the claim with the exception of explicitly disclosing forming a third electrode over the second electrode.
However, CHANG teaches a method of forming a semiconductor device including:
forming a second dielectric layer (340) over a second electrode (332);
forming a third conductive layer (350) over the second dielectric layer (340), wherein the third conductive layer (350) is a single layer of the polycrystalline material; and
patterning the third conductive layer (350) to form a third electrode (352). (See FIGs. 10A, 11).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of LIN further including forming the third conductive layer over the second dielectric layer as taught by CHANG for the same intended purpose of forming the capacitor structure with multiple electrodes, thus increasing the capacity of the semiconductor device.
With respect to claim 3, a first thickness of the first multi-layered structure (202) of LIN is the same as a second thickness of the second multi-layered structure (108), wherein, in view of CHANG, a third thickness of the third conductive layer (350) is the same as the first thickness (312).
With respect to claim 4, in view of SATO, before the plasma process, the first conductive layer (204a) of the first multi-layered structure (202) has a fourth thickness, wherein the second conductive layer (204b) of the first multi-layered structure (202) of CHANG has a fifth thickness equal to the fourth thickness.
With respect to claim 5, the fourth thickness of LIN is between about 100 Å and about 1000 Å, wherein the layer of the amorphous material (206) of the first multi-layered structure (202) has a thickness between about 10 Å and about 15 Å, hence overlap the claimed range of about 5 Å and about 10 Å.
With respect to claim 6, the first dielectric layer (208) and the second dielectric layer of LIN are formed of a high-k dielectric material.
With respect to claim 7, the first electrode (202) of LIN is formed to cover a first portion of the etch stop layer (106) and exposes a second portion of the etch stop layer, wherein the first dielectric layer (208) is formed conformally over the first electrode (202) and over the second portion of the etch stop layer.
With respect to claim 8, the second electrode (108) of LIN is formed to have a stair-shaped cross-section, wherein a first portion of the second electrode is laterally adjacent to the first electrode (202), and a second portion of the second electrode (108) extends along an upper surface of the first electrode distal from the substrate, wherein the second portion of the second electrode (108) exposes a first portion of the first dielectric layer (208) disposed along the upper surface of the first electrode (202).
With respect to claim 9, in view of CHANG, the third electrode (352) is formed to have a stair-shaped cross-section, wherein a first portion of the third electrode (352) is laterally adjacent to the second portion of the second electrode (332), and a second portion of the third electrode extends along an upper surface of the second portion of the second electrode distal from the substrate, wherein a first portion of the second dielectric layer (340) extends along the upper surface of the second portion of the second electrode (332), and is disposed laterally between opposing sidewalls of the second portion of the second electrode, wherein the second portion of the third electrode (352) covers a first region of the first portion of the second dielectric layer (340), and exposes a second region of the first portion of the second dielectric layer (340).
With respect to claim 10, in view of CHANG, the method further comprises, after patterning the third conductive layer (350): forming a passivation layer (370) over the third electrode (352) and the second dielectric layer (340), wherein the passivation layer (370) contacts and extends along the second region of the first portion of the second dielectric layer (340);
forming a first via (380) that extends through the first portion of the second electrode (332); and
forming a second via (380) that extends through the first portion of the third electrode (352) and the first electrode (312). (See FIG. 13).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over LIN ‘805 and SATO ‘493 as applied to claim 11 above, and further in view of LIN et al. (US. Pub. No. 2021/0091169) of record.
With respect to claim 12, LIN ‘805, in view of SATO’493, teaches the method as described in claim 11 above including: the plasma process is performed using nitrogen gas with a power of radio frequency (RF), and a duration of the plasma process is about 30 seconds, thus, within the claimed range of about 5 seconds and about 30 seconds.
Thus, LIN ‘805 and SATO are shown to teach all the features of the claim with the exception of explicitly disclosing the RF of about 30 W and about 300W.
However, LIN ‘169 teaches a method including performing a plasma process (1904) to treat an upper portion of a first conductive layer (1702), wherein a power of a radio frequency (RF) source used for the plasma process is between 30 W and about 300W, and a duration of the plasma process is between about 5 seconds and about 30 seconds.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to perform the plasma process of LIN ‘805, in view of SATO, using the RF power and the duration as taught by LIN ‘169 for the same intended purpose of amorphizing the upper surface of the conductive layer.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over LIN ‘805 and SATO ‘493 as applied to claim 1 above, and further in view of WU et al. (US. Pub. No. 2020/0075299) of record.
LIN ‘805, in view of SATO, teaches the method as described in claim 1 above including: the first conductive layer (204a) and the second conductive layer (204b) are formed using the same PVD process.
Thus, LIN ‘805 and SATO are shown to teach all the features of the claim with the exception of explicitly disclosing a deposition power of the PVD process is between about 1 KW and about 30 KW.
However, WU teaches a method of deposition an electrode utilizing PVD apparatus, wherein the deposition power of the PVD process is between 1 KW and about 30 KW. (See [0068]).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first and second conductive layer of LIN ‘805 utilizing the deposition power as taught by WU to avoid the production of ball defects.
Claims 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over LIN ‘805 in view of SATO ‘493 and CHANG ‘701.
With respect to claim 14, LIN teaches a method of forming a semiconductor device, substantially as claimed, the method comprising:
forming a transistor (308) over a substrate;
forming an etch stop layer (106) over the transistor and the substrate;
forming metal-insulator-metal (MIM) capacitor over an etch stop layer (106), including:
forming a bottom electrode (202) having a layered structure over the etch stop layer (106), wherein the bottom electrode (202) is formed to cover a first portion of the etch stop layer and expose a second portion of the etch stop layer (106), wherein forming the bottom electrode comprising:
forming a first layer of a polycrystalline material over the etch stop layer (106);
converting an upper portion of the first layer into a layer of amorphous material (206) using a treatment process; and
after the treatment process, forming a second layer of a polycrystalline material (204b) over the layer of the amorphous material (206), wherein the first layer of the polycrystalline material (204a) and the second layer of the polycrystalline material (204b) are formed by a same deposition method (PVD) and have a same thickness;
forming a first dielectric layer (208) over the second portion of the etch stop layer (106) and over the bottom electrode (202);
forming a middle electrode (108) over the first dielectric layer (208); and
forming a second dielectric layer over the middle electrode (108). (See FIGs. 2A-C, 7).
Thus, LIN is shown to teach all the features of the claim with the exception of explicitly disclosing converting the upper portion of the first layer into the layer of amorphous material utilizing a plasma process; and forming a top electrode over the second dielectric layer.
However, SATO teaches a method of forming a MIM capacitor including:
forming a first layer of a polycrystalline material (12) over an etch stop layer (11);
converting an upper portion of the first layer into a layer of amorphous material (33) using a plasma process; and
after the plasma process, forming a second layer of a polycrystalline material (37) over the layer of the amorphous material (33);
forming a first dielectric layer (15) over the second portion of the etch stop layer and over the bottom electrode (12);
forming a middle electrode (16) over the first dielectric layer (15). (See FIGs. 16A-17F).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to convert the upper portion of the first layer of LIN into the layer of amorphous material using a plasma process as taught by SATO for the same intended purpose of preventing diffusion of species into the capacitor dielectric layer.
Further, CHANG teaches a method of forming a semiconductor device including:
forming a bottom electrode (312) having a layered structure over an etch stop layer (308), wherein the bottom electrode (312) is formed to cover a first portion of the etch stop layer and expose a second portion of the etch stop layer, wherein forming the bottom electrode comprising:
forming a first layer of a polycrystalline material over the etch stop layer (106);
forming a first dielectric layer (320) over the second portion of the etch stop layer (308) and over the bottom electrode (312);
forming a middle electrode (332) over the first dielectric layer (320);
forming a second dielectric layer (340) over the middle electrode (332); and
forming a top electrode (352) over the second dielectric layer (340). See FIGs. 11).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of LIN, in view of SATO, further including forming the top electrode over the second dielectric layer as taught by CHANG for the same intended purpose of forming the MIM capacitor with multiple electrodes, thus increasing the capacity of the semiconductor device.
With respect to claim 15, the layer of the amorphous material (206) of the bottom electrode (202) of the bottom electrode of LIN ‘805 has a uniform thickness, and physically contact and extends along the first layer (204a) of the polycrystalline material of the bottom electrode (202) and the second layer (204b) of the polycrystalline material of the bottom electrode (202).
With respect to claim 16, in view of CHANG, a middle electrode (332) is formed to have the same layered structure as the bottom electrode (312), wherein the top electrode (352) is formed of a single layer of the polycrystalline material, wherein the bottom electrode (312), the middle electrode (332), and the top electrode (352) are formed to have the same thickness.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
With respect to claim 17, in view of CHANG, a first portion of the middle electrode (332) extends along an upper surface of the bottom electrode (312) distal from the substrate, wherein a first portion of the top electrode (352) extends along an upper surface of the first portion of the middle electrode (332) distal from the substrate, wherein the second dielectric layer (340) contacts and extends along the upper surface of the first portion of the middle electrode (332) and a sidewall of the first portion of the middle electrode, wherein the method further comprises:
forming a passivation layer (370) over the second dielectric layer (340) and the top electrode (352), wherein the passivation layer contacts and extends along a portion of the second dielectric layer (340) disposed along the sidewall of the first portion of the middle electrode (332);
forming a first via (380) that extends through the middle electrode (332); and
forming a second via (380) that extends through the bottom electrode (312) and the top electrode (352). (See FIG. 13).
With respect to claim 18, LIN teaches a method of forming a semiconductor device substantially as claimed, the method including:
forming a transistor (308) over a substrate;
forming an interconnect structure over the substrate;
forming an etch stop layer (510) over the interconnect structure;
forming a first multi-layered structure over the etch stop layer, comprising:
forming a first conductive layer over the etch stop layer, the first conductive layer comprising a polycrystalline material;
converting an upper portion of the first conductive layer into a second conductive layer (206) by performing a treatment process, the second conductive layer (206) comprising an amorphous material; and
forming a third conductive layer (204b) over the second conductive layer, the third conductive layer (204b) comprising the polycrystalline material, wherein the first conductive layer and the third conductive layer (204b) are formed to have a same thickness using a same formation method (PVD);
patterning the first multi-layered structure to form a first electrode (202);
forming a first high-k dielectric layer (208) over the first electrode (202);
forming a second multi-layered structure (108) over the first high-k dielectric layer (206), the second multi-layered structure (108) having the same layered structure as the first multi-layered structure (202);
patterning the second multi-layered structure to form a second electrode (108). (See FIGs. 2A-C, 7).
Thus, LIN is shown to teach all the features of the claim with the exception of explicitly disclosing converting the upper portion of the first conductive layer into the second conductive layer by performing a plasma process; and forming a third electrode over a second dielectric layer.
However, SATO teaches a method of forming a semiconductor device including:
forming a first conductive layer (12) over an etch stop layer (11), the first conductive layer (12) comprising a polycrystalline material;
converting an upper portion of the first conductive layer (12) into a second conductive layer (33) by performing a plasma process, the second conductive layer (33) comprising an amorphous material;
forming a third conductive layer (37) over the second conductive layer (33), the third conductive layer (37) comprising the polycrystalline material. (See FIGs. 16A-17F).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to convert the upper portion of the first conductive layer of LIN into the second conductive layer by performing the plasma process as taught by SATO for the same intended purpose of preventing diffusion of species into the capacitor dielectric layer.
Further, CHANG teaches a method of forming a semiconductor device including:
patterning a first multilayer structure (310b) to form a first electrode (312);
forming a first high-k dielectric layer (320) over the first electrode (312);
forming a second multi-layered structure (330b) over the first high-k dielectric layer (320), the second multi-layered structure (330b) having the same layered structure as the first multilayer structure (310b);
patterning the second multi-layered structure (310b) to form a second electrode (332);
forming a second high-k dielectric layer (340) over the second electrode (332);
forming a single layer of the polycrystalline material (350) over the second high-k dielectric layer (340); and
patterning the single layer of polycrystalline material (350) to form a third electrode (352). (See FIGs. 4B-11).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of LIN having the single layer of the polycrystalline material over the second high-k dielectric layer as taught by CHANG to increase the capacity of the MIM capacitor.
With respect to claim 19, the first conductive layer of LIN or CHANG is spaced apart from the third conductive layer (204b) by the second conductive layer (206), wherein the second conductive layer (206) contacts and extends along the first conductive layer and the third conductive layer (204b).
With respect to claim 20, As best understood by the Examiner, the first conductive layer, the second conductive layer (204b) of LIN, and the single layer of the polycrystalline material (352), in view of CHANG, are formed by the same formation method, wherein the first electrode (312), the second electrode (332), and the third electrode (352) are formed to have the same thickness.
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM.
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/ANH D MAI/Primary Examiner, Art Unit 2893
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