DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The IDS filed on July 23rd, 2024 has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor device comprising a first interconnect structure and a second interconnect structure and method.
Claim Objections
Claim 15 is objected to because of the following informalities: In claim 15, line 3, “a substrate” should be --a first substrate-- since claim 15 recites “a second substrate” on line 10. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5 and 8-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,148,664. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the claimed invention of the present application is encompassed by the scope of the claimed invention of U.S. Patent No. 12,148,664, see comparison below.
Claims of present application
Claims of U.S. Patent No. 12,148,664
1. A semiconductor device comprising: a substrate; a first interconnect structure over the substrate, the first interconnect structure comprising first dielectric layers and first metallization patterns; a through substrate via extending through the first interconnect structure and the substrate, the through substrate via comprising: a conductive material extending through the first interconnect structure and the substrate; a barrier layer between the first interconnect structure and the conductive material; and a liner between the conductive material and the substrate, wherein the liner physically contacts the substrate and the conductive material; a second interconnect structure over the first interconnect structure and the through substrate via, the second interconnect structure comprising second dielectric layers and second metallization patterns, the second metallization patterns of the second interconnect structure being electrically coupled to the first metallization patterns of the first interconnect structure and to the through substrate via; a third dielectric layer over the second interconnect structure; and bond pads in the third dielectric layer, the bond pads being electrically coupled to the second metallization patterns of the second interconnect structure.
8. A structure comprising: a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein; a through substrate via extending through the first interconnect structure and the first substrate, the through substrate via comprising: a conductive material extending through the first interconnect structure and the first substrate; a barrier layer between the first interconnect structure and the conductive material; and a liner between the conductive material and the first substrate, wherein the liner physically contacts the first substrate and the conductive material, the liner being an insulating layer extending from the first substrate to the conductive material; a second interconnect structure over the first interconnect structure and the through substrate via, the second interconnect structure comprising dielectric layers and metallization patterns therein, the metallization patterns of the second interconnect structure being electrically coupled to the metallization patterns of the first interconnect structure and to the through substrate via; a first dielectric layer over the second interconnect structure; first bond pads in the first dielectric layer, the first bond pads being electrically coupled to the metallization patterns of the second interconnect structure; and a package structure comprising a second substrate and a third interconnect structure over the second substrate, a second dielectric layer and second bond pads of the third interconnect structure being direct bonded to the first dielectric layer and first bond pads.
2. The semiconductor device of claim 1, wherein the barrier layer comprises silicon nitride.
10. The structure of claim 8, wherein the barrier layer is silicon nitride and wherein the liner is an oxide.
3. The semiconductor device of claim 1, wherein the liner comprises an oxide.
10. The structure of claim 8, wherein the barrier layer is silicon nitride and wherein the liner is an oxide.
4. The semiconductor device of claim 1, wherein the barrier layer physically contacts the first interconnect structure.
9. The structure of claim 8, wherein the barrier layer physically contacts the first interconnect structure.
5. The semiconductor device of claim 1, wherein the conductive material has a first width in the first interconnect structure and a second width in the substrate, the first width being greater than the second width.
13. The structure of claim 8, wherein the conductive material has a first width in the first interconnect structure and a second width in the first substrate, the first width being greater than the second width.
8. A method of forming a semiconductor device, the method comprising: forming a first interconnect structure over a substrate, the first interconnect structure comprising first dielectric layers and first metallization patterns; forming a first opening in the first interconnect structure; depositing a non-conformal barrier layer in the first opening; forming a second opening through the non-conformal barrier layer and into the substrate; depositing a liner in the first opening and the second opening; filling the first opening and the second opening with a conductive material to form a through substrate via; forming a second interconnect structure over the first interconnect structure and the through substrate via, the second interconnect structure comprising second dielectric layers and second metallization patterns; forming a third dielectric layer over the second interconnect structure; and forming bond pads in the third dielectric layer.
16. A method comprising: forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein; patterning the first interconnect structure to form a first opening exposing a portion of the first substrate; forming a passivation layer in the first opening; patterning the passivation layer in the first opening; etching a second opening in the first substrate using the patterned passivation layer as a mask; depositing a liner in the first opening and the second opening, the liner physically contacting the passivation layer; filling the first opening and the second opening with a conductive material; thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via; forming a second interconnect structure over the first interconnect structure and the through substrate via, the second interconnect structure comprising dielectric layers and metallization patterns therein, the metallization patterns of the second interconnect structure being electrically coupled to the metallization patterns of the first interconnect structure and to the through substrate via; forming a first dielectric layer over the second interconnect structure; and forming first bond pads in the first dielectric layer, the first bond pads being electrically coupled to the metallization patterns of the second interconnect structure.
9. The method of claim 8, wherein depositing the non-conformal barrier layer comprises performing a plasma-enhanced chemical vapor deposition (PECVD) process or a high density plasma CVD (HDP-CVD) process.
19. The method of claim 16, wherein forming the passivation layer comprises performing a plasma-enhanced chemical vapor deposition (PECVD) process, a high density plasma CVD (HDP-CVD), or a combination thereof, the passivation layer being a non-conformal layer.
10. The method of claim 8, wherein the non-conformal barrier layer forms an air gap in the first opening.
20. The method of claim 19, wherein after forming the passivation layer, the passivation layer has a void in the first opening.
11. The method of claim 8, wherein the second opening has a smaller diameter than the first opening.
Note that, a change in size is generally recognized as being within the level of ordinary skill in the art. See In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955), Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), and MPEP 2144.04.
12. The method of claim 8, further comprising thinning the substrate to expose a portion of the conductive material in the second opening.
16. A method comprising…filling the first opening and the second opening with a conductive material; thinning the first substrate to expose a portion of the conductive material in the second opening…
13. The method of claim 8, further comprising direct bonding the third dielectric layer and the bond pads to a package structure.
16. A method comprising…forming a first dielectric layer over the second interconnect structure; and forming first bond pads in the first dielectric layer, the first bond pads being electrically coupled to the metallization patterns of the second interconnect structure.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Su (U.S. Patent No. 10,651,157).
In re claim 15, Su discloses a semiconductor package comprising: a first semiconductor wafer 10 (see col. 4, line 55 and fig. 1C) comprising: a substrate 14 (see col. 4, line 61 and fig. 1C); a through substrate via structure 300 extending through the substrate 14 (see col. 5, line 20 and fig. 1C); an interconnect structure 144 over the substrate 14 and electrically coupled to the through substrate via 300 (see col. 5, lines 48-62 and fig. 1C); a dielectric layer 166 over the interconnect structure 144 (see col. 5, line 64 and fig. 1C); and first bond pads 164 in the dielectric layer 166 (see col. 5, line 65 and fig. 1C); a second semiconductor wafer 20 (see col. 4, line 56 and fig. 1C) comprising: a second substrate 24 (see col. 6, line 21 and fig. 1C); a second interconnect structure 244 over the second substrate 20 (see col. 6, lines 33-53 and fig. 1C); a second dielectric layer 266 over the second interconnect structure 244; and second bond pads 264 in the second dielectric layer 166 (see col. 6, lines 33-53 and fig. 1C); wherein the first bond pads 164 are directly bonded to the second bond pads 264, and wherein the first semiconductor wafer 10 and the second semiconductor wafer 20 are a same size (see col. 7, lines 7-17 and fig. 1C).
PNG
media_image1.png
528
788
media_image1.png
Greyscale
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su (U.S. Patent No. 10,651,157).
In re claim 16, as applied to claim 15 above, Su discloses in a current embodiment, wherein the through substrate via structure 300 comprises: a conductive material 330 extending through the substrate 14; and a liner 310 between the conductive material 330 and the substrate 14 (see col. 5, lines 20-47 and fig. 2) but is silent to a barrier layer between the interconnect structure and the conductive material.
However, in another embodiment, Su discloses a barrier layer 163 may be formed around an interconnection structure in order to prevent diffusion (see col. 6, lines 9-19 and fig. 2).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to be motivated to incorporate the technique as taught in another embodiment of Su into the current embodiment of Su in order to provide a barrier layer around the interconnect structure and thus the barrier layer would be located between the interconnect structure and the conductive material in order to prevent diffusion.
In re claim 17, as applied to claim 16 above, Su discloses wherein the barrier layer comprises silicon nitride and the liner 310 comprises an oxide (see col. 5, lines 30-31).
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su (U.S. Patent No. 10,651,157) in view of Suthiwongsunthorn et al. (U.S. Pub. 2009/0309235).
In re claim 18, as applied to claim 15 above, Su is silent to wherein the first semiconductor wafer is bonded to the second semiconductor wafer in a face-to-back configuration.
However, Suthiwongsunthorn discloses in a same field of endeavor, a semiconductor package, including, inter-alia, wherein the first semiconductor wafer can be bonded to the second semiconductor wafer in face-to-face or back-to-back configuration (see paragraph [0047]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to be motivated to incorporate the technique as taught by Suthiwongsunthorn into the semiconductor package of Su in order to enable wherein the first semiconductor wafer is bonded to the second semiconductor wafer in a face-to-back configuration in Su to be formed in order to improve functionality and provide high performance of the semiconductor package (see paragraph [0004] of Suthiwongsunthorn).
In re claims 19 and 20, as applied to claim 15 above, Su is silent to wherein the semiconductor package further comprising a redistribution structure over a back side of the first semiconductor wafer and electrically coupled to the through substrate via structure and further comprising conductive connectors on the redistribution structure.
However, Suthiwongsunthorn discloses in a same field of endeavor, a semiconductor package, including, inter-alia, wherein the semiconductor package further comprising a redistribution structure RDL over a back side of the first semiconductor wafer 100 and electrically coupled to the through substrate via structure 120 and further comprising conductive connectors 132 on the redistribution structure (see paragraphs [0032], [0035] and figs. 3D-F).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to be motivated to incorporate the technique as taught by Suthiwongsunthorn into the semiconductor package of Su in order to enable wherein the semiconductor package further comprising a redistribution structure over a back side of the first semiconductor wafer and electrically coupled to the through substrate via structure and further comprising conductive connectors on the redistribution structure in Su to be formed in order to improve functionality and provide high performance of the semiconductor package (see paragraph [0004] of Suthiwongsunthorn).
Allowable Subject Matter
Claims 6, 7, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin et al. (U.S. Pub. 2015/0021771) discloses a semiconductor device comprising: a substrate 200; a first interconnect structure 124a over the substrate 200, the first interconnect structure comprising first dielectric layers and first metallization patterns; a through substrate via 400 extending through the first interconnect structure and the substrate 200 (see paragraph [0027] and fig. 1D).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)272-1865. The examiner can normally be reached Monday-Friday 8:00 AM - 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
Prosecution Insights