Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stamper et al. (US 6,331,481).
Regarding claim 1, Stamper discloses a semiconductor structure, comprising:
a first conductive pattern (24) formed over a substrate (54/16), wherein the first conductive pattern (24) comprises a first conductive line (24/56) and a second conductive line (24/56) [Fig. 3E];
a barrier layer (26) formed over the first conductive line and over the second conductive line of the first conductive pattern [Fig. 3E];
an insulating layer (28) formed over the barrier layer [Fig. 3E]; and
a second conductive pattern (24) comprising a third conductive line (pattern between the two adjacent patterns 24/56) that is separated from the first conductive pattern by the barrier layer (26) [Fig. 3E].
Regarding claim 3, Stamper discloses wherein the barrier layer (26) comprises one or more of conformally deposited silicon nitride, silicon oxynitride, silicon carbide, and silicon carbide nitride [col. 6, lines 12-16].
Regarding claim 4, Stamper discloses wherein the insulating layer (28) further comprises one or more of silicon dioxide, silicon nitride, silicon carbide, undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, and combinations thereof [col. 6, lines 40-55].
Claims 1 and 4-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bonilla et al. (US 2018/0076133).
Regarding claim 1, Bonilla discloses a semiconductor structure, comprising:
a first conductive pattern (102 or 202) formed over a substrate (101 or 200), wherein the first conductive pattern (102 or 202) comprises a first conductive line (102, left outermost pattern; or 202) and a second conductive line (102, right outermost pattern; or 202) [Figs. 1D and 2];
a barrier layer (104 or 204) formed over the first conductive line and over the second conductive line of the first conductive pattern [Fig.1D and 2];
an insulating layer (106 or 206) formed over the barrier layer [Fig. 1D and 2]; and
a second conductive pattern (102 or 208) comprising a third conductive line that is separated from the first conductive pattern by the barrier layer (104 or 204) [Fig. 1D and 2].
Regarding claim 4, Bonilla discloses wherein the insulating layer (106 or 206) further comprises one or more of silicon dioxide, silicon nitride, silicon carbide, undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, and combinations thereof [paragraph 0037 and paragraph 0044].
Regarding claim 5, Bonilla discloses wherein the third conductive line comprises:
a conformally deposited metallic liner material comprising one or more of TiN, TaN, WN, TiC, TaC, and WC (210) [Fig. 2 and paragraph 0054]; and
a conformally deposited metallic fill material (208) comprising one or more of W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and combinations thereof [paragraph 0043].
Regarding claim 6, Bonilla discloses wherein the third conductive line (102, centered; or 208) is located between the first conductive line and the second conductive line and substantially fills a space between the first conductive line and the second conductive line [Fig. 1D and 2].
Regarding claim 7, Bonilla discloses wherein a separation (110) between the first conductive line (102 or 202) and the second conductive line (102 or 202) corresponds to a minimum feature spacing dictated by a resolution limit of an optical projection system that was used to generate the first conductive pattern [Figs. 1D and 2; and paragraphs 0038].
Claims 1, 3-5, and 11-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tyberg et al. (US 2010/0006850).
Regarding claim 1, Tyberg discloses a semiconductor structure, comprising:
a first conductive pattern (17/23/123) formed over a substrate (1), wherein the first conductive pattern (23/123) comprises a first conductive line (23) and a second conductive line (123) [Fig. 5];
a barrier layer (19/119/135/39) formed over the first conductive line and over the second conductive line of the first conductive pattern [Fig. 5 and paragraph 0079, 0081,0090, 0092];
an insulating layer (5/103) formed over the barrier layer [Fig. 5]; and
a second conductive pattern (25) comprising a third conductive line (25) that is separated from the first conductive pattern by the barrier layer [Fig. 5].
Regarding claim 3, Tyberg discloses wherein the barrier layer (19/119/135/39) comprises one or more of conformally deposited silicon nitride, silicon oxynitride, silicon carbide, and silicon carbide nitride [paragraph 0079, 0081,0090, 0092].
Regarding claim 4, Tyberg discloses wherein the insulating layer (5/103) further comprises one or more of silicon dioxide, silicon nitride, silicon carbide, undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, and combinations thereof [paragraph 0077].
Regarding claim 5, Tyberg discloses wherein the third conductive line (25) comprises:
a conformally deposited metallic liner material (19/27) comprising one or more of TiN, TaN, WN, TiC, TaC, and WC [Fig. 5and paragraph 0079]; and
a conformally deposited metallic fill material (25) comprising one or more of W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and combinations thereof [paragraph 0077].
Regarding claim 11, Tyberg discloses a semiconductor structure, comprising:
a first conductive pattern (17/23/123) formed over a substrate (1), wherein the first conductive pattern (23/123) comprises a first conductive line (23) and a second conductive line (123) [Fig. 5];
a barrier layer (19/119/135/39) formed over the first conductive line and over the second conductive line of the first conductive pattern [Fig. 5 and paragraph 0079, 0081,0090, 0092];
an insulating layer (5/103) formed over the barrier layer [Fig. 5];
a second conductive pattern (25) comprising a third conductive line (25) that is separated from the first conductive pattern by the barrier layer [Fig. 5]; and
a semiconductor layer (111) formed over the third conductive line and the barrier layer over the first conductive line and the second conductive line [Fig. 5].
Regarding claim 12, Tyberg discloses wherein the first conductive pattern (17/23/123) over a substrate further comprises a gate electrode (17) in a thin-film transistor (TFT) [Fig. 5 and paragraph 0089].
Regarding claim 13, Tyberg discloses wherein the barrier layer (19/119/135/39) formed over the first conductive pattern (17/23/123) further comprises a gate dielectric (39) in a thin-film transistor (TFT), such that the gate dielectric separates the first conductive pattern (17) from the semiconductor layer (111) [Fig. 5].
Regarding claim 14, Tyberg discloses wherein the gate dielectric (39) comprises high-k dielectric material [paragraph 0082].
Regarding claim 15, Tyberg discloses wherein the second conductive pattern (25) over a substrate further comprises a contact (13/113) in a thin-film transistor (TFT) [Fig. 5].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Stamper et al. (US 6,331,481).
Regarding claim 2, Stamper discloses wherein the barrier layer has a thickness in a range from 2 nm to 20 nm, from 3 nm to 12 nm, or from 5 nm to 10 nm [col. 6, lines 36-37]. The court has held that in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541F.2d 257,191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 7, discloses wherein a separation between the first conductive line and the second conductive line [Fig. 3E]. In regard to the limitation about “a minimum feature spacing dictated by a resolution limit of an optical projection system that was used to generate the first conductive pattern”, the method of forming the device as recited in the claim does not germane to the issue of patentability of the device itself. Therefore, this limitation has been given little patentable weight. Note that a "product by process" claim is directed to the product per se, no matter how actually made, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above case law makes clear.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Tyberg et al. (US 2010/0006850).
Regarding claims 7 and 17, discloses wherein a separation between the first conductive line (23) and the second conductive line (25) [Fig. 5]. In regard to the limitation about “a minimum feature spacing dictated by a resolution limit of an optical projection system that was used to generate the first conductive pattern”, the method of forming the device as recited in the claim does not germane to the issue of patentability of the device itself. Therefore, this limitation has been given little patentable weight. Note that a "product by process" claim is directed to the product per se, no matter how actually made, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above case law makes clear.
Allowable Subject Matter
Claims 8-10 are allowed.
Claims 16 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Dewey et al. (US 2020/0411692) teaches a TFT comprising gates (220), barrier (350), source/drain (250), and semiconductor channel layer (210).
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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/Jose R Diaz/Primary Examiner, Art Unit 2815
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