Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 9/9/2026. The changes and remarks disclosed therein have been considered. Claims 8, 17 have been cancelled by the amendment. Claims 1, 11 have been amended. Therefore, claims 1-7, 9-16, 18-20 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9-11, 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao PG PUB 20140016390 (hereinafter Zhao), in view of Baker PG PUB 20060187673 (hereinafter Baker).
Regarding independent claim 1, Zhao teaches a system comprising:
an array of resistive random access memory (RRAM) units arranged in rows and columns (figures 8-11 of Zhao, [0034] of Zhao, “…the invention proposes an electronic memory component comprising at least one two-dimensional matrix including in an integrated manner a plurality of unit memory cells, in particular binary, which are each realized at the intersection of a first conductor defining a column and a second conductor defining a row…”, [0036] of Zhao, “… RRAM (Resistor RAM) memories…”); and
a sense amplifier for determining a differential value stored in a first RRAM unit and a second RRAM unit in the array (Zhao’s sense amplifier compares resistance states of two complementary memory cells encoded in opposite states, thereby determining a differential value represented by the two cells, [0001] of Zhao, “…reading of the state of the cells by differential detection starting from two cells of two different rows...”, [0096] of Zhao, “…the read means comprise a plurality of detection amplifiers … arranged in order to carry out a differential reading from said two rows…”, [0200] of Zhao, “...each sense amplifier SA0 to SA3 supplies an output bit Bo0 to bo3 by comparing the resistance of one changeable MTJ with that of the other changeable MTJ which is complementary thereto. A storage bit is represented by two complementary cells which are encoded in two opposite states…”)
But Zhao does not teach a bias generator to apply a bias voltage during a read operation of the first RRAM unit and the second RRAM unit to compensate for offset.
However, Baker teaches offset-compensated sensing of resistive memory. Baker teaches a differential-amplifier circuit selectively operated in a calibration mode and a resistance measurement mode ([0035]-[0036]). During calibration, ab offset-compensation voltage representative of amplifier is stored, and when the circuit returns to resistance measurement mode, the stored voltage produces an inverse offset that negates the amplifier offset ([0037]). Baker further teaches that the compensated differential amplifier and transistor 70 maintain voltage Va on column line 30 and across resistive memory element 34 during the resistance measurement mode, with negative feedback correcting deviations caused by amplifier offset ([0039], figures 8-10).
Therefore, it would have been obvious to one of ordinary skill in the art to modify Zhao’s differential RRAM sensing circuitry to include Baker’s offset-compensated bias/voltage-generating circuitry so that the bias voltage applied during reading of Zhao first and second RRAM units is compensated for sensing-amplifier offset, thereby improving the accuracy and stability of the voltage applied to the resistive memory cells during sensing.
Regarding claim 9, the combination of Zhao and Baker teaches the system of claim 1, comprising a comparator ([0200] of Zhao, “...each sense amplifier SA0 to SA3 supplies an output bit Bo0 to bo3 by comparing the resistance of one changeable MTJ with that of the other changeable MTJ which is complementary thereto. A storage bit is represented by two complementary cells which are encoded in two opposite states…”)
Regarding claim 10, the combination of Zhao and Baker teaches the system of claim 9, wherein the sense amplifier receives a bias voltage to compensate for offset in the comparator by trimming an offset of the comparator (Zhao teaches the underlying RRAM differential sensing system and comparator/sense-amplifier functionality, Baker teaches offset compensated sensing for resistive memory, including a differential amplifier and compensation circuitry for compensation an offset associated with the differential amplifier. In particular, Baker teaches that offset within the differential amplifier cause the voltage on the sensing/read path to deviate from the desired reference voltage (figure 7, [0030]-[0033]). Baker further teaches an offset compensation circuit 148 associated with differential amplifier 146, including compensation transistors 150, 152 and compensation capacitors 172, 180 (figure 7, [0032]-[0033]). Baker explains that the compensation circuit compensates for offset within the differential amplifier, including offset caused by component asymmetry. More particularly, Baker teaches a calibration operation in which the differential amplifier is placed into a calibration configuration and an offset voltage is fed back and stored, such that the stored compensation voltage counteracts the amplifier offset during subsequent sensing (figures 8-10, [0035]-[0040]). Thus Baker teaches adjusting/trimming an offset of the sensing comparator/differential amplifier and providing the resulting compensation bias during the read operation. It would have been obvious to one of ordinary skill in the art to modify Zhao differential sense amplifier/comparator according to Baker’s offset-compensation technique to compensate amplifier/comparator offset and thereby improving the accuracy and reliability of differential sensing pf the RRAM cells).
Regarding independent claim 11, the combination of Zhao and Baker teaches a system comprising:
a first array (array formed by T20L/T10L/T00L and BL0L/BL1L in figure 11 of Zhao) of resistive random access memory (RRAM) units arranged in rows and columns (figures 8-11 of Zhao, [0034] of Zhao, “…the invention proposes an electronic memory component comprising at least one two-dimensional matrix including in an integrated manner a plurality of unit memory cells, in particular binary, which are each realized at the intersection of a first conductor defining a column and a second conductor defining a row…”, [0036] of Zhao, “… RRAM (Resistor RAM) memories…”);
a second array of RRAM units (array formed by T20R/T10R/T00R and BL0R/BL1R in figure 11 of Zhao) arranged in rows and columns; and
a sense amplifier for determining a differential value stored in a first RRAM unit in the first array and a second RRAM unit in the second array ([0001] of Zhao, “…reading of the state of the cells by differential detection starting from two cells of two different rows...”, [0096] of Zhao, “…the read means comprise a plurality of detection amplifiers … arranged in order to carry out a differential reading from said two rows…”, [0200] of Zhao, “...each sense amplifier SA0 to SA3 supplies an output bit Bo0 to bo3 by comparing the resistance of one changeable MTJ with that of the other changeable MTJ which is complementary thereto. A storage bit is represented by two complementary cells which are encoded in two opposite states…”)
a bias generator to apply a bias voltage during a read operation of the first RRAM unit and the second RRAM unit to compensate for offset (Baker teaches offset-compensated sensing of resistive memory. Baker teaches a differential-amplifier circuit selectively operated in a calibration mode and a resistance measurement mode ([0035]-[0036]). During calibration, ab offset-compensation voltage representative of amplifier is stored, and when the circuit returns to resistance measurement mode, the stored voltage produces an inverse offset that negates the amplifier offset ([0037]). Baker further teaches that the compensated differential amplifier and transistor 70 maintain voltage Va on column line 30 and across resistive memory element 34 during the resistance measurement mode, with negative feedback correcting deviations caused by amplifier offset ([0039], figures 8-10)).
Regarding claim 18, the combination of Zhao and Baker teaches the system of claim 11, comprising a comparator ([0200], “...each sense amplifier SA0 to SA3 supplies an output bit Bo0 to bo3 by comparing the resistance of one changeable MTJ with that of the other changeable MTJ which is complementary thereto. A storage bit is represented by two complementary cells which are encoded in two opposite states…”)
Regarding claim 19, the combination of Zhao and Baker teaches the system of claim 18, wherein the sense amplifier receives a bias voltage to compensate for offset in read path by trimming an offset of a comparator (Baker teaches compensating offset associated with the differential amplifier/comparator in the resistive -memory read path by determining an offset during calibration, storing a corresponding compensation voltage, and applying the compensation during subsequent resistance measurement/read operation (figure 7, [0030]-[0040]). Accordingly, it would have been obvious to modify Zhao’s differential RRAM sensing/read path according to Baker to compensate comparator offset and thereby improve the accuracy and reliability of read operation).
Claims 2-3, 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao PG PUB 20140016390 (hereinafter Zhao), in view of Baker PG PUB 20060187673 (hereinafter Baker), further in view of Yang PG PUB 20180218770 (hereinafter Yang).
Regarding claim 2, the combination of Zhao and Baker teaches the system of claim 1, but does not teach wherein the first RRAM unit comprises a first RRAM cell and a first select transistor.
Yang teaches in figure 1 a RRAM cell structure (104a-104d in figure 1 of Yang) include a first RRAM cell (106 in figure 1 of Yang, [0018] of Yang, “...an RRAM device 106 and an access transistor 108…”) and a first select transistor (108 in figure 1 of Yang).
Zhao, Baker and Yang are analogous art because they address the same field of endeavor: RRAM memory storage apparatuses control circuit designs and control methods. At the time of the effective filing, it would have been obvious to one of ordinary skill in the art, having the teachings of Zhao, Baker and Yang before him, recognizing the advantage of Zhao’s two-cell-1 bit method provides ([0200] of Zhao, “…allows a greater resistance difference between the two states of the storage bit, and therefore a better read reliability…”), would have been motived to adopt the 2 cell-1-bit scheme of Zhao in 1T1R cell configuration of Yang, such that the first RRAM unit (104a-104d in figure 1 of Yang) comprises a first RRAM cell and a first select transistor, in order to improve device performance.
Regarding claim 3, the combination of Zhao, Baker and Yang teaches the system of claim 2, wherein the second RRAM unit comprises a second RRAM cell and a second select transistor (Yang teaches each RRAM unit include an RRAM device and access transistor, see 104a-104d in figure 1 of Yang).
Regarding claim 12, the combination of Zhao, Baker and Yang teaches the system of claim 11, wherein the first RRAM unit comprises a first RRAM cell and a first select transistor (Yang teaches each RRAM unit include an RRAM device and access transistor, see 104a-104d in figure 1 of Yang).
Regarding claim 13, the combination of Zhao, Baker and Yang teaches the system of claim 12, wherein the second RRAM unit comprises a second RRAM cell and a second select transistor (Yang teaches each RRAM unit include an RRAM device and access transistor, see 104a-104d in figure 1 of Yang).
Claims 2, 4- 7, 12, 14, 15, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao PG PUB 20140016390 (hereinafter Zhao), in view of Baker PG PUB 20060187673 (hereinafter Baker), further in view of Yin US Patent 11107527 (hereinafter Yin).
Regarding claim 2, the combination of Zhao and Baker teaches the system of claim 1, but does not teach wherein the first RRAM unit comprises a first RRAM cell and a first select transistor.
Yin teaches in figure 2 a 1T1R cell structure and in figure 3 a 1T2R structure where the first RRAM unit (figure 2, 3 of Yin) comprises a first RRAM cell (RRAM device in figure 2, 3 of Yin) and a first select transistor (transistor in figure 2, 3 of Yin). The advantage of adopting 1T2R over 1T1R is to provide higher density, but at the expense of higher sneak current (Para(22), “…A 1T2R RRAM cell provides a higher density: only a single transistor is needed to control two RRAM devices. High density is a crucial performance metric for storage-class memory or other applications. Despite these technical advantages, challenges remain for implementing one or more 1T2R RRAM cells in a crossbar circuit, due to the existence of sneak current paths…”)
Zhao, Baker and Yin are analogous art because they address the same field of endeavor: RRAM memory storage apparatuses control circuit designs and control methods. At the time of the effective filing, it would have been obvious to one of ordinary skill in the art, having the teachings of Zhao, Baker and Yin before him, recognizing the advantage of Zhao’s two-cell-1 bit method provides ([0200] of Zhao, “…allows a greater resistance difference between the two states of the storage bit, and therefore a better read reliability…”), would have been motived to adopt the 2 cell-1-bit scheme of Zhao in 1T1R or 1T2R cell configuration of Yin, such that the first RRAM unit (figure 2, 3 of Yin) comprises a first RRAM cell and a first select transistor, in order to improve device performance.
Regarding claim 4, the combination of Zhao, Baker and Yin teaches the system of claim 2, wherein the second RRAM unit comprises a second RRAM cell, a third RRAM cell, and a second select transistor (Yin teaches in figure 3 each RRAM unit includes two RRAM devices and access transistor).
Regarding claim 5, the combination of Zhao, Baker and Yin teaches the system of claim 1, wherein the first RRAM unit comprises a first RRAM cell, a second RRAM cell, and a first select transistor (Yin teaches in figure 3 each RRAM unit includes two RRAM devices and access transistor).
Regarding claim 6, the combination of Zhao, Baker and Yin teaches the system of claim 5, wherein the first select transistor is connected to the first RRAM cell and the second RRAM cell (figure 3 of Yin, showing the common select transistor of 1T2R RRAM 303 connected to both RRAM devices).
Regarding claim 7, the combination of Zhao, Baker and Yin teaches the system of claim 6, wherein the second RRAM unit comprises a third RRAM cell, a fourth RRAM cell, and a second select transistor (Yin teaches a 1T2R RRAM configuration in which a single select transistor controls two RRAM devices. Yin explains that “1T2R RRAM cell provides a higher density: only a single transistor is needed to control two RRAM devices”. Accordingly, applying Yin’s 1T2R configuration to the second RRAM unit of Zhao provides the claimed third RRAM cell, fourth RRAM cell, and second select transistor).
Regarding claim 12, the combination of Zhao, Baker and Yin teaches the system of claim 11, wherein the first RRAM unit comprises a first RRAM cell and a first select transistor (Yin teaches in figure 3 each RRAM unit includes two RRAM devices and access transistor).
Regarding claim 14, the combination of Zhao, Baker and Yin teaches the system of claim 12, wherein the second RRAM unit comprises a second RRAM cell, a third RRAM cell, and a second select transistor (Yin teaches in figure 3 each RRAM unit includes two RRAM devices and access transistor).
Regarding claim 15, the combination of Zhao, Baker and Yin teaches the system of claim 11, wherein the first RRAM unit comprises a first RRAM cell, a second RRAM cell, and a first select transistor (Yin teaches in figure 3 each RRAM unit includes two RRAM devices and access transistor).
Regarding claim 16, the combination of Zhao, Baker and Yin teaches the system of claim 15, wherein the second RRAM unit comprises a third RRAM cell, a fourth RRAM cell, and a second select transistor (Yin teaches in figure 3 each RRAM unit includes two RRAM devices and access transistor).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/XIAOCHUN L CHEN/Primary Examiner, Art Unit 2824
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