Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
Applicant's election without traverse of Group I, including claims 1-19, in the reply filed on 02/03/2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first select transistor recited in claims 5, 6 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121 (d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as "amended." If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either "Replacement Sheet" or "New".
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 6 recites, “the first select transistor is connected to the first RRAM unit and the second RRAM unit”, claim 6 is dependent on claim 5, claim 5 recites, “the first RRAM unit comprises a first RRAM cell, a second RRAM cell, and a first select transistor”. Therefore, it seems that claim 5 makes the select transistor part of the first unit, claim 6 then treat the select transistor as something external to the first unit and connected to it. It is unclear whether the first select transistor is part of the first RRAM unit or is separate from and connected to the first RRAM unit. Accordingly, the mates and bounds of the claimed “first RRAM unit” cannot be determined with reasonable certainty, thus renders this limitation vague and indefinite.
Regarding claims 6-7, no art is being applied at this time with regarding to the claims due to the nature of the 112 set forth above.
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Examiner Notes: Although no art is used against the claims, this is not an indication that the application is allowable. The 112 problem causes a great deal of confusion and uncertainty as to the proper interpretation of the limitation of the claims. It is difficult for the examiner to ascertain what the applicant feels is the claimed invention. Prior art rejections will be on hold until and unless clarification is made.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9, 11, 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao PG PUB 20140016390 (hereinafter Zhao).
Regarding independent claim 1, Zhao teaches a system comprising:
an array of resistive random access memory (RRAM) units arranged in rows and columns (figures 8-11, [0034] of Zhao, “…the invention proposes an electronic memory component comprising at least one two-dimensional matrix including in an integrated manner a plurality of unit memory cells, in particular binary, which are each realized at the intersection of a first conductor defining a column and a second conductor defining a row…”, [0036], “… RRAM (Resistor RAM) memories…”); and
a sense amplifier for determining a differential value stored in a first RRAM unit and a second RRAM unit in the array (Zhao’s sense amplifier compares resistance states of two complementary memory cells encoded in opposite states, thereby determining a differential value represented by the two cells, [0001], “…reading of the state of the cells by differential detection starting from two cells of two different rows...”, [0096], “…the read means comprise a plurality of detection amplifiers … arranged in order to carry out a differential reading from said two rows…”, [0200], “...each sense amplifier SA0 to SA3 supplies an output bit Bo0 to bo3 by comparing the resistance of one changeable MTJ with that of the other changeable MTJ which is complementary thereto. A storage bit is represented by two complementary cells which are encoded in two opposite states…”)
Regarding claim 9, Zhao teaches the system of claim 1, comprising a comparator ([0200], “...each sense amplifier SA0 to SA3 supplies an output bit Bo0 to bo3 by comparing the resistance of one changeable MTJ with that of the other changeable MTJ which is complementary thereto. A storage bit is represented by two complementary cells which are encoded in two opposite states…”)
Regarding independent claim 11, Zhao teaches a system comprising:
a first array (array formed by T20L/T10L/T00L and BL0L/BL1L in figure 11) of resistive random access memory (RRAM) units arranged in rows and columns (figures 8-11, [0034] of Zhao, “…the invention proposes an electronic memory component comprising at least one two-dimensional matrix including in an integrated manner a plurality of unit memory cells, in particular binary, which are each realized at the intersection of a first conductor defining a column and a second conductor defining a row…”, [0036], “… RRAM (Resistor RAM) memories…”);
a second array of RRAM units (array formed by T20R/T10R/T00R and BL0R/BL1R in figure 11) arranged in rows and columns; and
a sense amplifier for determining a differential value stored in a first RRAM unit in the first array and a second RRAM unit in the second array ([0001], “…reading of the state of the cells by differential detection starting from two cells of two different rows...”, [0096], “…the read means comprise a plurality of detection amplifiers … arranged in order to carry out a differential reading from said two rows…”, [0200], “...each sense amplifier SA0 to SA3 supplies an output bit Bo0 to bo3 by comparing the resistance of one changeable MTJ with that of the other changeable MTJ which is complementary thereto. A storage bit is represented by two complementary cells which are encoded in two opposite states…”)
Regarding claim 18, Zhao teaches the system of claim 11, comprising a comparator ([0200], “...each sense amplifier SA0 to SA3 supplies an output bit Bo0 to bo3 by comparing the resistance of one changeable MTJ with that of the other changeable MTJ which is complementary thereto. A storage bit is represented by two complementary cells which are encoded in two opposite states…”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao PG PUB 20140016390 (hereinafter Zhao), in view of Yang PG PUB 20180218770 (hereinafter Yang).
Regarding claim 2, Zhao teaches the system of claim 1, but does not teach wherein the first RRAM unit comprises a first RRAM cell and a first select transistor.
Yang teaches in figure 1 a RRAM cell structure (104a-104d in figure 1 of Yang) include a first RRAM cell (106 in figure 1 of Yang, [0018] of Yang, “...an RRAM device 106 and an access transistor 108…”) and a first select transistor (108 in figure 1 of Yang).
Zhao and Yang are analogous art because they address the same field of endeavor: RRAM memory storage apparatuses control circuit designs and control methods. At the time of the effective filing, it would have been obvious to one of ordinary skill in the art, having the teachings of Zhao and Yang before him, recognizing the advantage of Zhao’s two-cell-1 bit method provides ([0200] of Zhao, “…allows a greater resistance difference between the two states of the storage bit, and therefore a better read reliability…”), would have been motived to adopt the 2 cell-1-bit scheme of Zhao in 1T1R cell configuration of Yang, such that the first RRAM unit (104a-104d in figure 1 of Yang) comprises a first RRAM cell and a first select transistor, in order to improve device performance.
Regarding claim 3, the combination of Zhao and Yang teaches the system of claim 2, wherein the second RRAM unit comprises a second RRAM cell and a second select transistor (Yang teaches each RRAM unit include an RRAM device and access transistor, see 104a-104d in figure 1 of Yang).
Regarding claim 12, the combination of Zhao and Yang teaches the system of claim 11, wherein the first RRAM unit comprises a first RRAM cell and a first select transistor (Yang teaches each RRAM unit include an RRAM device and access transistor, see 104a-104d in figure 1 of Yang).
Regarding claim 13, the combination of Zhao and Yang teaches the system of claim 12, wherein the second RRAM unit comprises a second RRAM cell and a second select transistor (Yang teaches each RRAM unit include an RRAM device and access transistor, see 104a-104d in figure 1 of Yang).
Claims 2, 4, 5, 12, 14, 15, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao PG PUB 20140016390 (hereinafter Zhao), in view of Yin US Patent 11107527 (hereinafter Yin).
Regarding claim 2, Zhao teaches the system of claim 1, but does not teach wherein the first RRAM unit comprises a first RRAM cell and a first select transistor.
Yin teaches in figure 2 a 1T1R cell structure and in figure 3 a 1T2R structure where the first RRAM unit (figure 2, 3 of Yin) comprises a first RRAM cell (RRAM device in figure 2, 3 of Yin) and a first select transistor (transistor in figure 2, 3 of Yin). The advantage of adopting 1T2R over 1T1R is to provide higher density, but at the expense of higher sneak current (Para(22), “…A 1T2R RRAM cell provides a higher density: only a single transistor is needed to control two RRAM devices. High density is a crucial performance metric for storage-class memory or other applications. Despite these technical advantages, challenges remain for implementing one or more 1T2R RRAM cells in a crossbar circuit, due to the existence of sneak current paths…”)
Zhao and Yin are analogous art because they address the same field of endeavor: RRAM memory storage apparatuses control circuit designs and control methods. At the time of the effective filing, it would have been obvious to one of ordinary skill in the art, having the teachings of Zhao and Yin before him, recognizing the advantage of Zhao’s two-cell-1 bit method provides ([0200] of Zhao, “…allows a greater resistance difference between the two states of the storage bit, and therefore a better read reliability…”), would have been motived to adopt the 2 cell-1-bit scheme of Zhao in 1T1R or 1T2R cell configuration of Yin, such that the first RRAM unit (figure 2, 3 of Yin) comprises a first RRAM cell and a first select transistor, in order to improve device performance.
Regarding claim 4, the combination of Zhao and Yin teaches the system of claim 2, wherein the second RRAM unit comprises a second RRAM cell, a third RRAM cell, and a second select transistor (Yin teaches in figure 3 each RRAM unit include two RRAM devices and access transistor).
Regarding claim 5, the combination of Zhao and Yin teaches the system of claim 1, wherein the first RRAM unit comprises a first RRAM cell, a second RRAM cell, and a first select transistor (Yin teaches in figure 3 each RRAM unit include two RRAM devices and access transistor).
Regarding claim 12, the combination of Zhao and Yin teaches the system of claim 11, wherein the first RRAM unit comprises a first RRAM cell and a first select transistor (Yin teaches in figure 3 each RRAM unit include two RRAM devices and access transistor).
Regarding claim 14, the combination of Zhao and Yin teaches the system of claim 12, wherein the second RRAM unit comprises a second RRAM cell, a third RRAM cell, and a second select transistor (Yin teaches in figure 3 each RRAM unit include two RRAM devices and access transistor).
Regarding claim 15, the combination of Zhao and Yin teaches the system of claim 11, wherein the first RRAM unit comprises a first RRAM cell, a second RRAM cell, and a first select transistor (Yin teaches in figure 3 each RRAM unit include two RRAM devices and access transistor).
Regarding claim 16, the combination of Zhao and Yin teaches the system of claim 15, wherein the second RRAM unit comprises a third RRAM cell, a fourth RRAM cell, and a second select transistor (Yin teaches in figure 3 each RRAM unit include two RRAM devices and access transistor).
Claims 8, 10, 17, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao PG PUB 20140016390 (hereinafter Zhao), in view of Maffitt US Patent 10726897 (hereinafter Maffitt).
Regarding claim 8, Zhao teaches the system of claim 1, but does not teach wherein the sense amplifier receives a bias voltage to compensate for offset in the array.
Maffitt teaches compensating offset and mismatch associated with a memory sensing circuit by applying trim circuitry to the sense amplifier. Specifically, Maffitt teaches that mismatch between devices in the sense amplifier causes sensing errors and reduce read margin and further teaches trim circuitry configured to compensate such mismatch and offset (col3, lines 34-58, col 4 lines 1-27), Maffitt further teaches trim elements and trim control circuitry that modify the operating point of the sense amplifier to cancel mismatch-induced offset and improving sensing accuracy (figure 1B, 3, 4, col 4-6, Abstract, “…circuit further includes a reference trim circuitry and a data trim circuitry configured to correct for device mismatch errors…”, trim circuitry modifies the operating point of the sense amplifier and thus supplies a compensated bias voltage).
One of the ordinary skills in the art would have found it obvious to modify Zhao’s sense amplifier to receive a bias/trim voltage as taught by Moffitt in order to compensate for offset and device mismatch.
Regarding claim 10, the combination of Zhao and Maffitt teaches the system of claim 9, wherein the sense amplifier receives a bias voltage to compensate for offset in the comparator by trimming an offset of a comparator (Maffitt teaches offset compensation for a sensing circuit including a comparator. Specifically, Maffitt teaches a comparator 140 (figure 1A, 1B) and teaches trim circuitry (Rtrim_ref, Rtrim_data) configured to compensate device mismatch and offset errors occurring in the sensing oath prior to comparator evaluation, see col 3, lines 34-58, col 4, lines 1-27, col 5, lines 33-67, figures 3, 4). Maffitt further teaches configurable trim elements (TRIMX<1>-TRIMX<7>) that adjust the sense amplifier operating point and cancel offset errors before generation of the comparator output. Because comparator 140 generates the final sensing output and form part of the sensing circuit, compensation of mismatch and offset errors in the sensing circuit necessarily compensate offset errors affecting comparator evaluation).
Regarding claim 17, the combination of Zhao and Maffitt teaches the system of claim 11, wherein the sense amplifier receives a bias voltage to compensate for offset in the array (figure 1B, 3, 4, col 4-6, Abstract, “…circuit further includes a reference trim circuitry and a data trim circuitry configured to correct for device mismatch errors…”, trim circuitry modifies the operating point of the sense amplifier and thus supplies a compensated bias voltage).
Regarding claim 19, the combination of Zhao and Maffitt teaches the system of claim 18, wherein the sense amplifier receives a bias voltage to compensate for offset in read path by trimming an offset of a comparator (Maffitt teaches offset compensation for a sensing circuit including a comparator. Specifically, Maffitt teaches a comparator 140 (figure 1A, 1B) and teaches trim circuitry (Rtrim_ref, Rtrim_data) configured to compensate device mismatch and offset errors occurring in the sensing oath prior to comparator evaluation, see col 3, lines 34-58, col 4, lines 1-27, col 5, lines 33-67, figures 3, 4). Maffitt further teaches configurable trim elements (TRIMX<1>-TRIMX<7>) that adjust the sense amplifier operating point and cancel offset errors before generation of the comparator output. Because comparator 140 generates the final sensing output and form part of the sensing circuit, compensation of mismatch and offset errors in the sensing circuit necessarily compensate offset errors affecting comparator evaluation).
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
Prosecution Insights