DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 19-26 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/18/2026.
Applicant’s election without traverse of Group I, claims 1-18 in the reply filed on 03/18/2026 is acknowledged.
Drawings
The drawings are objected to because the character “BI0” in Fig. 8 should be “BL0”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
The transistor “808” in paragraph [0042], line 9 should be “806”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitations “a first voltage” in line 4 and “a second voltage” in line 5. It is unclear whether these limitations are different from “a first voltage” recited in claim 1, line 8 and “a second voltage” in line 9.
Claim Objections
Claim 11 is objected to because of the following informalities:
The word “for” before “a second row of memory cells” should be “of”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tran et al. (US 2016/0133639 hereinafter “Tran”).
Regarding claim 1, Tran (Fig. 3) shows a system comprising:
an array (paragraph [0002]) of non-volatile memory cells arranged into rows and columns, each non- volatile memory cell comprising a first bit line terminal (paragraph [0036], line 8, DRA is connected to a bit line), a first erase gate terminal (16 left), a first control gate terminal (14 left), a first floating gate (12 left), a word line (26), a second floating gate (12 right), a second control gate terminal (14 right), a second erase gate terminal (16 right), and a second bit line terminal (DRB), wherein the first floating gate can store a first digital or analog value and the second floating gate can store a second digital or analog value (it is inherent that each floating gate is used to store a digital or analog value); and
a bit line decoder (Fig. 32, 60) for a column to selectively provide a first voltage to the first bit line terminals of non-volatile memory cells in the column and a second voltage to the second bit line terminals of the non-volatile memory cells in the column.
Paragraph [0057] discloses a bit line decoder 60 used to decode addresses and supply the various voltages to the above lines during read, program and erase operations for selected memory cells.
Regarding claim 4, Tran discloses the system of claim 1, comprising:
a row decoder for a row to selectively provide a third voltage to word line terminals of non-volatile memory cells in the row, to selectively provide a fourth voltage to first control gate terminals of the non-volatile memory cells in the row, to selectively provide a fifth voltage to second control gate terminals of the non-volatile memory cells in the row, to selectively provide a sixth voltage to first erase gate terminals of the non-volatile memory cells in the row, and to selectively provide a seventh voltage to second erase gate terminals of the non-volatile memory cells in the row.
Paragraph [0055] discloses a row decoder 56 used to decode addresses and supply the various voltages to the above lines during read, program and erase operations for selected memory cells.
Regarding claim 5, Tran discloses the system of claim 4, wherein the row decoder comprises a word line decoder to generate the third voltage (paragraph [0055]).
Regarding claim 6, Tran discloses the system of claim 4, wherein the row decoder comprises a control gate decoder to generate the fourth voltage and the fifth voltage (paragraph [0055]).
Regarding claim 7, Tran discloses the system of claim 4, wherein the row decoder comprises an erase gate decoder to generate the sixth voltage and the seventh voltage (paragraph [0055]).
Regarding claim 8, Tran discloses the system of claim 7, wherein one or more of the sixth voltage and the seventh voltage is a positive voltage (Fig. 8, VEGE).
Regarding claim 9, Tran discloses the system of claim 7, wherein one of more of the fourth voltage and the fifth voltage is a negative voltage.
Regarding claim 10, Tran (Figs. 3 and 28) shows a system comprising:
an array of non-volatile memory cells (Fig. 28) arranged into rows and columns, each non- volatile memory cell comprising a first bit line terminal, a first erase gate terminal, a first control gate terminal, a first floating gate, a word line, a second floating gate, a second control gate terminal, a second erase gate terminal, and a second bit line terminal, wherein the first floating gate can store a first digital or analog value and the second floating gate can store a second digital or analog value (Fig. 3);
wherein each column in the array contains a first bitline coupled to first bit line
terminals of non-volatile memory cells in the column and a second bitline coupled to second bit line terminals of non-volatile memory cells in the column (Fig. 28).
Regarding claim 11, Tran shows the system of claim 10, wherein erase gate terminals of a first row of memory cells is coupled to erase gate terminals for a second row of memory cells (EG1 is connected to the erase gate terminals of the first row (M1, M3, M9 and M11) and the erase gate terminals of the second row (M4, M6, M12 and M14).
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tran et al. (US 2016/0293260, cited in the IDS filed on 12/16/2024, hereinafter Tran ‘260).
Regarding claim 1, Tran ‘260 (Fig. 28) shows a system comprising:
an array of non-volatile memory cells arranged into rows and columns, each non- volatile memory cell comprising a first bit line terminal, a first erase gate terminal (EG0), a first control gate terminal (CG0_A), a first floating gate, a word line (WL0), a second floating gate, a second control gate terminal (CG0_B), a second erase gate terminal (EG1), and a second bit line terminal (BL1), wherein the first floating gate can store a first digital or analog value and the second floating gate can store a second digital or analog value (it is inherent that each floating gate is used to store a digital or analog value); and
a bit line decoder (Fig. 32, 60) for a column to selectively provide a first voltage to the first bit line terminals of non-volatile memory cells in the column and a second voltage to the second bit line terminals of the non-volatile memory cells in the column.
Paragraph [0074] discloses a bit line decoder 60 used to decode addresses and supply the various voltages to the above lines during read, program and erase operations for selected memory cells.
Regarding claim 2, Tran ‘260 (Fig. 46) discloses the system of claim 1, wherein the bit line decoder comprises for each column a first pair of transistors coupled to the first bit line terminal and a second pair of transistors coupled to the second bit line terminal, the first pair comprising a first transistor coupled to a first voltage and a second transistor coupled to ground and the second pair comprising a third transistor coupled to a second voltage and a fourth transistor coupled to ground.
Regarding claims 4-11, Tran ‘260 discloses all the limitations as recited in claims 4-11 (see Fig. 32 and Fig. 27).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tran in view of Wang et al. (US 2019/0214396, hereinafter “Wang”).
Claim 12-18 differ from Tran in reciting that a pair of adjacent columns in the array contains a first bitline coupled to first bit line terminals of non-volatile memory cells in the first column, a second bitline coupled to first bit line terminals of non-volatile memory cells in the second column and a third bitline coupled to second bit line terminals of non-volatile memory cells in the first column and to second bit line terminals of non-volatile memory cells in the second column. However, Wang (Fig. 5) shows a pair of adjacent columns (BLn-2 and BLn) in the array contains a first bitline (BLn2-2) coupled to first bit line terminals of non-volatile memory cells in the first column, a second bitline (BLn) coupled to first bit line terminals of non-volatile memory cells in the second column and a third bitline (BLn-1) coupled to second bit line terminals of non-volatile memory cells in the first column and to second bit line terminals of non-volatile memory cells in the second column. I would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use the configurations of Wang into the memory device of Tran to reduce the surface area space occupied by each pair of memory cells (paragraph [0004]).
Regarding claim 13, Wang discloses when the second portion (second floating gate) is to be read, a bit line (an unselected bit line BLs) adjacent to the first bit line receives a bias voltage (0V) (paragraph [0032] and Table 2)
Regarding claims 14 and 15, Wang discloses when the first portion (first floating gate) is to be read, a bit line (an unselected bit line BLs) adjacent to the first bit line is shorted to ground (0V) (paragraph [0032] and Table 2)
Regarding claim 16, Wang discloses when the second portion (second floating gate) is to be programmed, a bit line (an unselected bit line BLs) adjacent to the second bit line receives a bias voltage (0V) (paragraph [0032] and Table 2)
Regarding claims 17 and 18, Wang discloses when the first portion (first floating gate) is to be programmed, a bit line (an unselected bit line BLs) adjacent to the first bit line is shorted to ground (0V) (paragraph [0032] and Table 2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUAN HOANG whose telephone number is (571)272-1779. The examiner can normally be reached 7:30AM-4:00PM M-F.
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/HUAN HOANG/ Primary Examiner, Art Unit 2827
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