DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Amendment filed on 06/30/2026 has been received and entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 4-9 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. (US 2016/0133639 hereinafter "Tran" cited in the previous office action) in view of McCrate et al. (US 2022/0130447, hereinafter “McCrate”).
Regarding claim 1, Tran (Figs. 28 and 28) shows a system comprising:
an array (paragraph [0002]) of non-volatile memory cells (Fig. 3, CELL #6) arranged into rows and columns, each non- volatile memory cell (CELL #6) comprising a first bit line terminal (BL0), a first erase gate terminal (EG0), a first control gate terminal (CG0_A), a first floating gate (under CG0_A), a word line (WL0), a second floating gate (under CG0_B), a second control gate terminal (CG0_B), a second erase gate terminal (EG1), and a second bit line terminal (DRB), wherein the first floating gate can store a first digital or analog value and the second floating gate can store a second digital or analog value (it is inherent that each floating gate is used to store a digital or analog value); and
a bit line decoder (Fig. 32, 60) for a column (paragraph [0055], line 9, each column has two drains connected to BL0 and BL1) to selectively provide a first voltage to the first bit line terminals of non-volatile memory cells in the column and a second voltage different than the first voltage to the second bit line terminals of the non-volatile memory cells in the column (Fig. 28 and Fig. 30, Fig. 30 shows in the program operation or read operation, the voltage of the bit line BL0 is different from the voltage of the bit line BL1).
Paragraph [0055] discloses a bit line decoder 60 used to decode addresses and
supply the various voltages to the above lines during read, program and erase
operations for selected memory cells.
Tran discloses each CELL #6 comprises a pair of cells to store data but does not disclose each non-volatile memory cell comprising two bit line terminals, two erase gate terminals, two floating gate terminals and two control gate terminals.
However, McCrate discloses the first memory cell 124 and the second memory cell 127 represent two physical memory cells that map to a single memory cell (paragraph [0028]) and map the first memory cell and the second memory cell to the same column address (paragraph [0033]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to map two physical memory cells to a single logical memory cell to store a single bit.
Regarding claim 4, Tran discloses the system of claim 1, comprising:
a row decoder for a row to selectively provide a third voltage to word line
terminals of non-volatile memory cells in the row, to selectively provide a fourth voltage
to first control gate terminals of the non-volatile memory cells in the row, to selectively
provide a fifth voltage to second control gate terminals of the non-volatile memory cells
in the row, to selectively provide a sixth voltage to first erase gate terminals of the non-
volatile memory cells in the row, and to selectively provide a seventh voltage to second
erase gate terminals of the non-volatile memory cells in the row.
Paragraph [0055] discloses a row decoder 56 used to decode addresses and
supply the various voltages to the above lines during read, program and erase
Regarding claim 5, Tran discloses the system of claim 4, wherein the row
decoder comprises a word line decoder to generate the third voltage (paragraph
[0055]).
Regarding claim 6, Tran discloses the system of claim 4, wherein the row
decoder comprises a control gate decoder to generate the fourth voltage and the fifth
voltage (paragraph [0055]).
Regarding claim 7, Tran discloses the system of claim 4, wherein the row
decoder comprises an erase gate decoder to generate the sixth voltage and the seventh
voltage (paragraph [0055]).
Regarding claim 8, Tran discloses the system of claim 7, wherein one or more of
the sixth voltage and the seventh voltage is a positive voltage (Fig. 8, VEGE).
Regarding claim 9, Tran discloses the system of claim 7, wherein one of more of
the fourth voltage and the fifth voltage is a negative voltage.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Tran ‘260 in view of McCrate.
Regarding claim 1, Tran '260 (Fig. 28) shows a system comprising:
an array of non-volatile memory cells arranged into rows and columns, each pair of non-volatile memory cells comprising a first bit line terminal, a first erase gate terminal (EG0), a first control gate terminal (CG0_A), a first floating gate, a word line (WL0), a second floating gate, a second control gate terminal (CG0_B), a second erase gate terminal (EG1), and a second bit line terminal (BL1), wherein the first floating gate can store a first digital or analog value and the second floating gate can store a second digital or analog value (it is inherent that each floating gate is used to store a digital or analog value); and a bit line decoder (Fig. 32, 60) for a column to selectively provide a first voltage to the first bit line terminals of non-volatile memory cells in the column and a second voltage different than the first voltage to the second bit line terminals of the non-volatile memory cells in the column (Fig. 30).
Tran discloses each CELL #6 comprises a pair of cells to store data but does not disclose each non-volatile memory cell comprising two bit line terminals, two erase gate terminals, two floating gate terminals and two control gate terminals.
However, McCrate discloses the first memory cell 124 and the second memory cell 127 represent two physical memory cells that map to a single memory cell (paragraph [0028]) and map the first memory cell and the second memory cell to the same column address (paragraph [0033]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to map two physical memory cells to a single logical memory cell to store a single bit.
Regarding claim 2, Tran '260 (Fig. 46) discloses the system of claim 1, wherein
the bit line decoder comprises for each column a first pair of transistors coupled to the first bit line terminal and a second pair of transistors coupled to the second bit line
terminal, the first pair comprising a first transistor coupled to a first voltage and a second
transistor coupled to ground and the second pair comprising a third transistor coupled to
a second voltage and a fourth transistor coupled to ground.
Regarding claim 3, the fifth transistor is only the equalization circuit that is well-known in the art to provide the same voltage to a pair of bit lines.
Regarding claims 4-9, Tran '260 discloses all the limitations as recited in claims
4-11 (see Fig. 32 and Fig. 27).
Claims 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tran in view McCrate applied to claim 1 above, and further in view of Wang et al. (US 2019/0214396, cited in the previous office action, hereinafter "Wang").
Claim 13-18 differ from Tran in view of McCrate in reciting that a pair of adjacent columns in the array contains a first bitline coupled to first bit line terminals of non-volatile memory cells in the first column, a second bitline coupled to first bit line terminals of non-volatile memory cells in the second column and a third bitline coupled to second bit line terminals of non-volatile memory cells in the first column and to second bit line terminals of non-volatile memory cells in the second column. However, Wang (Fig. 5) shows a pair of adjacent columns (BLn-2 and BLn) in the array contains a first bitline (BLn2-2) coupled to first bit line terminals of non-volatile memory cells in the first column, a second bitline (BLn) coupled to first bit line terminals of non-volatile memory cells in the second column and a third bitline (BLn-1) coupled to second bit line terminals of non-volatile memory cells in the first column and to second bit line terminals of non-volatile memory cells in the second column. I would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use the configurations of Wang into the memory device of Tran to reduce the surface area space occupied by each pair of memory cells (paragraph [0004]).
Regarding claim 13, Wang discloses when the second portion (second floating
gate) is to be read, a bit line (an unselected bit line BLs) adjacent to the first bit line
receives a bias voltage (OV) (paragraph [0032] and Table 2)
Regarding claims 14 and 15, Wang discloses when the first portion (first floating
gate) is to be read, a bit line (an unselected bit line BLs) adjacent to the first bit line is
shorted to ground (OV) (paragraph [0032] and Table 2)
Regarding claim 16, Wang discloses when the second portion (second floating
gate) is to be programmed, a bit line (an unselected bit line BLs) adjacent to the second
bit line receives a bias voltage (OV) (paragraph [0032] and Table 2)
Regarding claims 17 and 18, Wang discloses when the first portion (first floating
gate) is to be programmed, a bit line (an unselected bit line BLs) adjacent to the first bit
line is shorted to ground (OV) (paragraph [0032] and Table 2).
Response to Arguments
Applicant’s arguments with respect to claims 1-9 and 13-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUAN HOANG whose telephone number is (571)272-1779. The examiner can normally be reached 7:30AM-4:00PM M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUAN HOANG/Primary Examiner, Art Unit 2827
Prosecution Insights