DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/24/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15-18 and 20 of U.S. Patent No. 12,191,251 in view of Chen (US 2019/0131273).
Regarding claim 1, Pat '251 discloses, in claim 15, a method of forming a semiconductor package, the method comprising:
forming a redistribution structure on a carrier; attaching an integrated passive device to a first side of the redistribution structure; after attaching the integrated passive device, removing the carrier; and attaching a semiconductor device to a second side of the redistribution structure, wherein the redistribution structure is between the semiconductor device and the integrated passive device ("a redistribution structure on a carrier; attaching an integrated passive device to the redistribution structure; attaching an interconnect structure to the redistribution structure using solder joints, the integrated passive device being between two of the solder joints; after attaching the interconnect structure, removing the carrier; and attaching a semiconductor device to the redistribution structure, wherein the redistribution structure is between the semiconductor device and the integrated passive device", in claim 15 of Pat '251, is interpreted as the same limitation).
Pat '251 does not explicitly disclose the integrated passive device is electrically coupled to the semiconductor device.
Chen teaches, in at least figure 5 and related text, the method comprising the integrated passive device (101, [41]) is electrically coupled to the semiconductor device (300, [25]), for the purpose of reducing physical size of a package thereby improving density of integration ([1]-[2]).
Pat '251 and Chen are analogous art because they are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '251 with the specified features of Chen because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '251 to have the integrated passive device being electrically coupled to the semiconductor device, as taught by Chen, for the purpose of reducing physical size of a package thereby improving density of integration ([1]-[2], Chen).
Regarding claim 2, Pat '251 in view of Chen discloses the method of claim 1 as described above.
Chen further teaches, in at least figure 5 and related text, attaching an interconnect structure (RDL1, [23]) to the first side of the redistribution structure (RDL2, [23]), the integrated passive device (101, [41]) being between the interconnect structure (RDL1, [23]) and the redistribution structure (RDL2, [23]), for the purpose of reducing physical size of a package thereby improving density of integration ([1]-[2]).
Regarding claim 3, Pat '251 in view of Chen discloses the method of claim 2 as described above.
Pat '251 further discloses, in claim 15, attaching the interconnect structure to the redistribution structure is performed using solder joints ("attaching an interconnect structure to the redistribution structure using solder joints", in claim 15 of Pat '251, is interpreted as the same limitation).
Regarding claim 4, Pat '251 in view of Chen discloses the method of claim 3 as described above.
Pat '251 further discloses, in claim 15, the integrated passive device is between two of the solder joints ("the integrated passive device being between two of the solder joints", in claim 15 of Pat '251, is interpreted as the same limitation).
Regarding claim 5, Pat '251 in view of Chen discloses the method of claim 2 as described above.
Pat '251 further discloses, in claim 16, forming an insulating material along sidewalls of the interconnect structure (all limitations are the same with the limitations recited in 16 of Pat '251).
Chen further teaches, in at least figure 5 and related text, the insulating material (E1, [21]) extending along sidewalls of the integrated passive device (101, [41]), for the purpose of reducing physical size of a package thereby improving density of integration ([1]-[2]).
Regarding claim 6, Pat '251 in view of Chen discloses the method of claim 5 as described above.
Pat '251 further discloses, in claim 17, after attaching the interconnect structure, singulating through the redistribution structure and the insulating material (all limitations are the same with the limitations recited in 17 of Pat '251).
Chen further teaches, in at least figure 5 and related text, sidewalls of the redistribution structure (RDL2, [23]) being free of the insulating material (E1, [21]), for the purpose of reducing physical size of a package thereby improving density of integration ([1]-[2]).
Regarding claim 7, Pat '251 in view of Chen discloses the method of claim 6 as described above.
Pat '251 further discloses, in claim 18, after singulating, a portion of the insulating material remains along sidewalls of the interconnect structure (all limitations are the same with the limitations recited in 18 of Pat '251).
Regarding claim 8, Pat '251 in view of Chen discloses the method of claim 1 as described above.
Pat '251 further discloses, in claim 20, a distance between the integrated passive device and the semiconductor device is less than 0.3 mm (all limitations are the same with the limitations recited in 20 of Pat '251).
Claims 16-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 14 and 20 of U.S. Patent No. 11,715,686 in view of Chen (US 2019/0131273).
Regarding claim 16, Pat '686 discloses, in claim 14 and 20, a method of forming a semiconductor package, the method comprising:
forming a redistribution structure on a carrier, the redistribution structure comprising first contact pads at a first side adjacent the carrier, redistribution structure comprising second contact pads at a second side distal from the carrier; attaching an integrated device to the second contact pads of the redistribution structure; removing the carrier and exposing the first contact pads of the redistribution structure; and attaching a semiconductor device of the first contact pads of the redistribution structure ("forming a redistribution structure on a carrier, the redistribution structure comprising first contact pads at a first side adjacent the carrier, redistribution structure comprising second contact pads at a second side distal from the carrier; attaching an integrated passive device to the second contact pads of the redistribution structure; attaching an interconnect structure to the second contact pads of the redistribution structure, the interconnect structure completely covering the integrated passive device interposed between the redistribution structure and the interconnect structure; removing the carrier and exposing the first contact pads of the redistribution structure; and attaching a semiconductor device of the first contact pads of the redistribution structure", in claim 14 of Pat '686, is interpreted as the same limitation), wherein a distance between the integrated device and the semiconductor device is less than 0.3 mm (“a distance between the integrated passive device and the semiconductor device is less than 0.3 mm", in claim 20 of Pat '686, is interpreted as the same limitation).
Pat '686 does not explicitly disclose the integrated device is electrically coupled to the semiconductor device.
Chen teaches, in at least figure 5 and related text, the method comprising the integrated device (101, [41]) is electrically coupled to the semiconductor device (300, [25]), for the purpose of reducing physical size of a package thereby improving density of integration ([1]-[2]).
Pat '686 and Chen are analogous art because they are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '686 with the specified features of Chen because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '686 to have the integrated device being electrically coupled to the semiconductor device, as taught by Chen, for the purpose of reducing physical size of a package thereby improving density of integration ([1]-[2], Chen).
Regarding claim 17, Pat '686 in view of Chen discloses the method of claim 16 as described above.
Chen further teaches, in at least figure 5 and related text, attaching a plurality of interconnect structures (RDL1 under 101/ RDL1 under 201, [23], figure) to the second contact pads of the redistribution structure (RDL2, [23]), a first interconnect structure (RDL1 under 101, [23], figure) of the plurality of the interconnect structure (RDL1 under 101/ RDL1 under 201, [23], figure) covering the integrated device (101, [41]), for the purpose of reducing physical size of a package thereby improving density of integration ([1]-[2]).
Regarding claim 18, Pat '686 in view of Chen discloses the method of claim 17 as described above.
Chen further teaches, in at least figure 5 and related text, forming an encapsulant (E1, [21]) over the plurality of interconnect structures (RDL1 under 101/ RDL1 under 201, [23], figure), the encapsulant extending between the first interconnect structure (RDL1 under 101, [23], figure) and the redistribution structure (RDL1 under 201, [23], figure), for the purpose of reducing physical size of a package thereby improving density of integration ([1]-[2]).
Claim 19 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 14 and 20 of U.S. Patent No. 11,715,686 in view of Chen (US 2019/0131273), and further in view of Koey (US 2016/0086930).
Regarding claim 19, Pat '686 in view of Chen discloses the method of claim 18 as described above.
Pat '686 in view of Chen does not explicitly disclose the encapsulant extends between the first interconnect structure and the integrated device.
Koey teaches, in at least figures 1, 3, and related text, the method comprising the encapsulant (58, [20]) extends between the first interconnect structure (36, [15]) and the integrated device (28(a)/28(b)/28(c), [13]), for the purpose of embedding multiple levels or layers of microelectronic components in a back-to-back relationship in the molded package body thereby increasing density of device ([12]).
Pat '686, Chen, and Koey are analogous art because they are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '686 in view of Chen with the specified features of Koey because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '686 in view of Chen to have the encapsulant extending between the first interconnect structure and the integrated device, as taught by Koey, for the purpose of embedding multiple levels or layers of microelectronic components in a back-to-back relationship in the molded package body thereby increasing density of device ([12], Koey).
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 14 and 20 of U.S. Patent No. 11,715,686 in view of Chen (US 2019/0131273), Koey (US 2016/0086930), and further in view of claims 17-18 of U.S. Patent No. 12,191,251.
Regarding claim 20, Pat '686 in view of Chen and Koey discloses the method of claim 19 as described above.
Pat '686 in view of Chen and Koey does not explicitly disclose after forming the encapsulant, singulating through the redistribution structure and the encapsulant, wherein, after singulating, a portion of the encapsulant remains along sidewalls of the first interconnect structure.
Pat '251 teaches, in claims 17 and 18, after forming the encapsulant, singulating through the redistribution structure and the encapsulant, wherein, after singulating, a portion of the encapsulant remains along sidewalls of the first interconnect structure ("after attaching the interconnect structure, singulating through the redistribution structure and the insulating material" and “after singulating, a portion of the insulating material remains along sidewalls of the interconnect structure”, in claims 17 and 18 of Pat '251, are interpreted as the same limitation), for the purpose of providing package structures for high functional density with relatively low cost and high performance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '686 in view of Chen and Koey to have after forming the encapsulant, the singulating through the redistribution structure and the encapsulant, wherein, after singulating, a portion of the encapsulant remains along sidewalls of the first interconnect structure, as taught by Pat '251, for the purpose of providing package structures for high functional density with relatively low cost and high performance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chen (US 2019/0131273).
Regarding claim 1, Chen discloses, in at least figures 1A-1G, 4, and related text, a method of forming a semiconductor package, the method comprising:
forming a redistribution structure (RDL2, [22]) on a carrier (C, [14]);
attaching an integrated passive device (101, [41]) to a first side of the redistribution structure (RDL2, [22]);
after attaching the integrated passive device (101, [41]), removing the carrier (C, [14]); and
attaching a semiconductor device (300, [25]) to a second side of the redistribution structure (RDL2, [22]), wherein the redistribution structure (RDL2, [22]) is between the semiconductor device (300, [25]) and the integrated passive device (101, [41]), wherein the integrated passive device (101, [41]) is electrically coupled to the semiconductor device (300, [25]).
Regarding claim 2, Chen discloses the method of claim 1 as described above.
Chen further discloses, in at least figures 1A-1G, 4, and related text, attaching an interconnect structure (RDL1, [23]) to the first side of the redistribution structure (RDL2, [23]), the integrated passive device (101, [41]) being between the interconnect structure (RDL1, [23]) and the redistribution structure (RDL2, [23]).
Allowable Subject Matter
Claims 9-15 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 9 that recite "forming a first underfill material extending along sidewalls of the integrated device and the first interconnect structure" in combination with other elements of the base claims 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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