DETAILED ACTION
Allowable Subject Matter
Claims 22, 32 & 40 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Claim 22 recites in part “while the conductive structure has a bottom surface reaching on a doped region”. The closest prior art Examiner has found is EP-0243034, FIGs. 2 and 2A. The prior art does show “conductive structure” 30, which has a bottom surface reaching on “a doped region” 34. However, Examiner has no clue how to argue for the case of obviousness of combination in the instant case. Hence, indication of allowable subject matter.
Claims 32 & 40 contain broadly similar limitations and therefore are indicated as allowable for broadly similar reasons.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21, 23-31 and 33-39 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by (US-2020/0127025) by Lim et al (“Lim”).
Regarding claim 21, Lim discloses in FIGs. 7-9 and related text, e.g., a semiconductor device, comprising:
a substrate (FIG. 9, 100) having an active region (“IA”) and a peripheral region (“CA”) arranged next to the active region;
a plurality of pixels (FIG. 8, Px; see FIG. 7, 910 and related text) arranged in the active region and respectively comprising a photosensitive region (200) and a circuitry region (300) next to the photosensitive region;
a conductive grid (FIGs. 8-9, 450) disposed in the active region and separating the plurality of pixels one from another (see FIG. 8); and
a conductive structure disposed within the peripheral region (FIG. 8, 450 in “CA” area), wherein the conductive grid is electrically connected to the conductive structure (see FIG. 8; 450 is all interconnected, since it is all one reference number).
Regarding claim 23, Lim discloses in FIGs. 7-9 and related text, e.g., further comprising a metal layer (FIG. 8, 450 in “BA” area) connecting top surfaces of the conductive structure (450 in “CA” area) and conductive grid (450 in “IA” area).
Regarding claim 24, Lim discloses in FIGs. 7-9 and related text, e.g., wherein the conductive grid comprises metal columns (see FIG. 9; 450 is all columns) extended into the peripheral region (450 is in all regions), and the metal layer is retained within the peripheral region (450 is retained within every region; hence, peripheral region too; thus meeting limitations).
Regarding claim 25, Lim discloses in FIGs. 7-9 and related text, e.g., wherein the conductive grid is in a form of solid bulk (450 qualifies as solid bulk in FIG. 9); and
wherein the conductive structure is in a form of a conformal layer with which a dielectric material is disposed between opposing sidewalls of the conductive structure (450 is also conformally formed with dielectric material 410 on opposite sidewalls in FIG. 9; hence, “conformal layer”).
Regarding claim 26, Lim discloses in FIGs. 7-9 and related text, e.g., further comprising:
an interconnect structure (FIG. 9, 500) disposed under the active region,
wherein the conductive structure (450) is disposed through the substrate (100) and electrically connected to a metal line of the interconnect structure (by definition; all 450 is connected to negative bias (see par. 137, etc.); and various transistors also need negative bias by definition; hence, such wiring (with negative bias) would be present throughout “interconnect structure”; and the two would be electrically connected to each other, since they are both at negative bias (otherwise known as “ground”), and
wherein the conductive grid is electrically connected to the metal line of the interconnect structure via the conductive structure (by definition; “grid” would get its connection to “negative bias” from some pad; hence, on the way to the pad, the “conductive structure” is in-between; on the other hand, the “interconnect structure” would get its “negative bias” also from “pad”; hence, the path would be “interconnect structure” [Wingdings font/0xE0] “pad” [Wingdings font/0xE0] “conductive structure” [Wingdings font/0xE0] “grid”; thus meeting limitations; at the very least such limitations are obvious due to the need to have outside connection (like 800 in FIG. 9) in order to get negative bias into the chip in the first place; and thus such limitations are at the very least obvious).
Regarding claim 27, Lim discloses in FIGs. 7-9 and related text, e.g., wherein the conductive grid is laterally overlapped with the circuitry region (see FIG. 9).
Regarding claim 28, Lim discloses in FIGs. 7-9 and related text, e.g., a semiconductor device, comprising:
a substrate having an active region and a peripheral region next to the active region (see claim 21);
an interconnect disposed along a first side of the substrate (see claim 26; bottom side in FIG. 9);
a plurality of pixels arranged in the active region and respectively comprising a photosensitive region and a circuitry region next to the photosensitive region and electrically connected to the interconnect (see claim 21, and electrical connections in FIG. 9);
a conductive grid disposed in the active region and separating the plurality of pixels one from another (see claim 21); and
a conductive structure disposed within the peripheral region, wherein the conductive grid and the conductive structure are connected by a metal layer disposed along a second side of the substrate opposite to the first side (see claims 21 & 23; top side of FIG. 9; please note that 450 has a surface along the top surface of 100).
Regarding claim 29, Lim discloses in FIGs. 7-9 and related text, e.g., wherein the conductive grid is electrically connected to a metal line of the interconnect through the conductive structure (see claim 26).
Regarding claim 30, Lim discloses in FIGs. 7-9 and related text, e.g., wherein the conductive grid extends from the second side into a position within the substrate from the second side and separates from the interconnect by a dielectric layer (sidewalls are covered by 410 which is insulating; bottom is covered by another insulator [Wingdings font/0xE0] best marked in FIG. 11E, 521; also, see FIG. 13C).
Regarding claim 31, Lim discloses in FIGs. 7-9 and related text, e.g., wherein the conductive structure extends from the second side and electrically connects to the interconnect from the first side (it electrically connects to sources of negative bias from every side; bottom too; see claim 26).
Regarding claim 33, Lim discloses in FIGs. 7-9 and related text, e.g., wherein the conductive grid is laterally overlapped with the circuitry region (see FIG. 9).
Regarding claim 34, Lim discloses in FIGs. 7-9 and related text, e.g., wherein the conductive grid, the conductive structure, and the metal layer are of the same material (they are all 450; hence, same material).
Regarding claim 35, Lim discloses in FIGs. 7-9 and related text, e.g., wherein the conductive grid has bottom and sidewall surfaces covered by a dielectric material (see claim 30), while the conductive structure (see 450 on the right most side of FIG. 9) has a bottom surface reaching on a conductive component (890 is close to the bottom surface of right most 450; hence, meeting limitations).
Regarding claim 36, Lim discloses in FIGs. 7-9 and related text, e.g., wherein the conductive grid comprises metal columns extended into the peripheral region, and the metal layer is retained within the peripheral region (see claim 24; same logic applies).
Regarding claim 37, Lim discloses in FIGs. 7-9 and related text, e.g., wherein the conductive grid is in a form of solid bulk; and
wherein the conductive structure is in a form of a conformal layer with which a dielectric material is disposed between opposing sidewalls of the conductive structure (see claim 25; same logic applies).
Regarding claim 38, Lim discloses in FIGs. 7-9 and related text, e.g., a semiconductor device, comprising:
a substrate having an active region and a peripheral region next to the active region (see claim 21);
an interconnect disposed along a first side of the substrate (see claim 26; bottom side of substrate in FIG. 9);
a plurality of pixels arranged in the active region and respectively comprising a photosensitive region and a circuitry region next to the photosensitive region and electrically connected to the interconnect (see claim 28);
a conductive grid disposed in the active region and separating the plurality of pixels one from another (see claim 28); and
a conductive structure disposed within the peripheral region, wherein the conductive grid is electrically connected to the conductive structure (see claim 28),
wherein the conductive grid extends from a second side of the substrate opposite to the first side and terminates at a position within the substrate (see claim 30 and FIG. 13C for example of 450 that terminates within the substrate).
Regarding claim 39, Lim discloses in FIGs. 7-9 and related text, e.g., wherein the conductive grid and the conductive structure are electrically connected from the second side (they are electrically connected from every side; by definition).
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
09/24/26
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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