DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 14-19 of U.S. Patent No. 10,886,226. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations presented have already been recited in USP10886226.
Regarding claim 1, USP10886226 recites the limitation of a method, comprising:
forming an opening that extends partially through an interlayer dielectric (ILD) structure (dielectric), wherein the opening is vertically aligned with, but does not expose, a source/drain component (claim 16, column 15, lines 46-48 and claim 14, lines 20-22);
extending the opening downwards vertically through a plurality of deposition-etching cycles until the source/drain component is exposed, wherein each of the deposition-etching cycles deposits a respective barrier layer in the opening and etches the opening further downwards vertically (claim 14, column 15, lines 23-35); and
forming a source/drain contact in the opening after the deposition-etching cycles have been performed (claim 16, column 47, which teaches that this opening is over the source/drain region and claim 14, column 15, lines 36-40, in which the conductive material is used to form the source/drain contact).
Regarding claim 2, USP10886226 recites the limitation of the deposition-etching cycles are performed within a single fabrication tool (claim 15).
Regarding claim 3, USP10886226 recites the limitation of the source/drain component includes an epi-layer; and the deposition-etching cycles are performed until the opening exposes the epi-layer (claim 8 and claim 14, wherein the opening exposes the epi-layer is generally performed in order to form a conductive contact to the source/drain region).
Regarding claim 4, USP10886226 recites the limitation of the deposition-etching cycles comprise a first deposition process that deposits a first barrier layer, followed by a first etching process, followed by a second deposition process that deposits a second barrier layer on the first barrier layer, followed by a second etching process (claim 16, column 16, lines 1-15).
Regarding claim 5, USP10886226 recites the limitation of the deposition-etching cycles are performed such that a side surface of the second barrier layer extends to a side surface of the first barrier layer and a side surface of the ILD (claim 16, column 16, lines 1-15).
Regarding claim 6, USP10886226 recites the limitation of the first deposition process and the second deposition process deposit different materials as the first barrier layer and the second barrier layer (claim 18)
Regarding claim 7, USP10886226 recites the limitation of the first deposition process deposits TaN as the first barrier layer, and the second deposition process deposits Ta, Ti, or TiN as the second barrier layer (claim 19).
Regarding claim 8, USP10886226 recites the limitation of the deposition-etching cycles further comprise: a third deposition process that deposits a third barrier layer followed by a third etching process that extends the opening downwardly vertically until the source/drain component is exposed (Claim 16, column 16, lines 16-25, wherein the opening exposes the epi-layer is generally performed in order to form a conductive contact to the source/drain region)
Regarding claim 9, USP10886226 recites the limitation of in at least some of the deposition-etching cycles, a removal process is performed between the deposition and the etching, wherein the removal process removes a portion of the barrier layer deposited by the deposition onto a bottom surface of the opening, such that bottom surface of the opening is uncovered by the barrier layer (column 16, lines 5-24).
Regarding claim 10, USP10886226 recites the limitation of the removal process includes a resputtering process (claim 15, lines 31-35).
Regarding claim 11, USP10886226 recites the limitation of forming the source/drain contact comprises depositing a conductive material in the opening, and wherein the method further comprises performing an annealing process before the conductive material is deposited in the opening (claim 17).
Regarding claim 12, USP10886226 recites the limitation of the conductive material is deposited such that a side surface of the conductive material extends to a last one of the barrier layers deposited into the opening by the deposition-etching cycles (claim 14, lines 36-40).
Regarding claim 13, USP10886226 recites the limitations of a method, comprising:
etching a recess in an electrically-insulating structure (dielectric material), wherein the recess is disposed over, but does not expose, a source/drain component (claim 16, column 15, lines 46-48 and claim 14, lines 20-22);
performing a plurality of deposition-etching cycles until the source/drain component is exposed by the recess, wherein in each of the deposition-etching cycles, a respective barrier layer is deposited in the recess, and thereafter the recess is etched further downwards (claim 14, column 15, lines 23-35); and
forming a source/drain contact in the recess after the deposition-etching cycles have been performed, wherein a side surface of the source/drain contact is formed to extend to a side surface of the barrier layer deposited by a last cycle of the deposition-etching cycles (claim 16, column 47, which teaches that this opening is over the source/drain region and claim 14, column 15, lines 36-40, in which the conductive material is used to form the source/drain contact).
Regarding claim 14, USP10886226 recites the limitation of the deposition-etching cycles deposit a first barrier layer having a first depth, a second barrier layer having a second depth greater than the first depth, and a third barrier layer having a third depth greater than the second depth (claim 16, column 16, lines 1-24)..
Regarding claim 15, USP10886226 recites the limitation of the side surface of the source/drain contact extends to a side surface of the third barrier layer (claim 16, column 16, lines 1-25).
Regarding claim 16, USP10886226 recites the limitation of in between a deposition step and an etching step of each of the deposition-etching cycles, a resputtering process is performed, and wherein the resputtering process removes a portion of the barrier layer deposited by the deposition step, such that the electrically-insulating structure is exposed by the recess (claim 15, lines 23-35).
Regarding claim 17, USP10886226 recites the limitation of the first barrier layer, the second barrier layer, and the third barrier layer are deposited using different materials (claim 18).
Regarding claim 18, USP10886226 recites the limitations of a method, comprising:
etching an opening in an electrically-insulating structure (dielectric material), wherein the opening is aligned with, but does not extend to, a source/drain component that includes an epi-layer (claim 16, column 15, lines 46-48, claim 14, lines 20-22, and claim 8);
extending the opening vertically downward by performing at least two process cycles, wherein each of the two process cycles includes a deposition step that deposits a respective barrier layer in the opening, as well as an etching step that further etches the opening into the electrically-insulating structure after the barrier layer has been deposited, and wherein the opening is extended vertically until the source/drain component is reached (claim 14, column 15, lines 23-35); and
forming a source/drain contact in the opening, wherein a depth of the source/drain contact exceeds respective depths of at least a subset of the barrier layers (claim 16, column 47, which teaches that this opening is over the source/drain region and claim 14, column 15, lines 36-40, in which the conductive material is used to form the source/drain contact).
Regarding claim 19, USP10886226 recites the limitation of the at least two process cycles comprise three process cycles or four process cycles (claim 16, column 16, lines 1-24).
Regarding claim 20, USP10886226 recites the limitation of barrier layers having different material compositions are deposited by the at least two process cycles (claim 18).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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QVJ
/DALE E PAGE/ Supervisory Patent Examiner, Art Unit 2899
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