DETAILED ACTION
This Office action is in response to the Preliminary Amendment filed on 20 August 2024. Claims 2-21 are pending in the application. Claim 1 has been cancelled. Claims 2-21 are newly submitted.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 is confusing because it is unclear if the first and second strips required in claim 11 correspond to the semiconductor fin required in independent claim 2, from which claim 11 depends.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 18-20 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Sung et al., US 2015/0021696.
With respect to claim 18, Sung et al. disclose a device, shown in Fig. 6, comprising:
a semiconductor fin 20 (between openings 36, as shown in Fig. 3);
a gate stack 24/26/28/34 over the semiconductor fin 20, as shown in Fig. 6; and
a source/drain region 38/42 aside of the semiconductor fin 20, as shown in Fig. 6,
wherein the source/drain region comprises: a first semiconductor layer 38 comprising a first top surface comprising a first facet (see paragraph [0014]);
a second semiconductor layer (lower portion of layer 42) over the first semiconductor layer 38 and contacting the first facet to form a first interface,
wherein the second semiconductor layer comprises a second top surface 43 comprising a second facet; and
a third semiconductor layer (upper portion of layer 42) over the second semiconductor layer (lower portion of layer 42) and contacting the second facet to form a second interface,
wherein in a cross-sectional view of the device, the first interface and the second interface are joined at a same point (the outermost corner of gate spacer 34), as shown in Fig. 6.
With respect to claim 19, in the device of Sung et al., the same point is a top corner of the semiconductor fin 20, see Figs. 3 and 6.
With respect to claim 20, in the device of Sung et al., one of the first interface and the second interface is on a (111) surface plane (see paragraph [0014]) of a respective layer of the first semiconductor layer 38 and the second semiconductor layer (lower portion of layer 42), see .Figs. 3 and 6 and paragraph [0014].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Sung et al., US 2015/0021696, as applied to claim 18 above, and further in view of Li et al., US 2019/0097006.
With respect to claim 21, Sung et al. is applied as above. Sung lacks anticipation of the first semiconductor layer 38, the second semiconductor layer (the lower portion of layer 42), and the third semiconductor layer (the upper portion of layer 42) comprise silicon phosphorus, and wherein the second semiconductor layer has a higher phosphorus concentration than the firs semiconductor layer and the third semiconductor layer. Sung et al. disclose that source/drain regions 38/42 are doped p-type, but Sung et al. do teach that layer 42 has a greater boron concentration than layer 38, see paragraphs [0017] and [0018]. In the same field of endeavor, Li et al. disclose a raised source/drain region 220 comprising a first semiconductor layer 220-1 comprising a boron concentration of 5 x 1019 atoms/cm3, see paragraph [0028], a second semiconductor layer 220-2 comprising a boron concentration of 1 x 1020 atoms/cm3, see paragraph [0028]) higher than the first dopant concentration (5 x 1019 atoms/cm3, see paragraph [0028]), and a third semiconductor layer 220-3 comprising a boron concentration of concentration (5 x 1019 atoms/cm3, see paragraph [0035]) lower than the second dopant concentration (1 x 1020 atoms/cm3, see paragraph [0028]). Given this disclosure of Li et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second semiconductor layer (the lower portion of layer 42) could have a higher dopant concentration than the first semiconductor layer 38 and the third semiconductor layer (the upper portion of layer 42) in the known device of Sung et al.
Admittedly, both Sung et al. and Li et al. disclose boron-doped epitaxial source/drain regions. However, in paragraphs [0020] and [0021], Li et al. disclose that the fabricated device can be an N-type MOSFET or an N-type FinFET. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the dopant used in the known device of Sung et al. in view of Li et al. could have been phosphorus in order to fabricate an N-type MOSFET or an N-type FinFET, since phosphorus is a well-known n-type dopant, as taught by Sung et al. in paragraph [0011]. It is clearly within the purview of one skilled in the art to that phosphorus can be doped into the source/drain region 38/42 of Sung et al.to yield an N-type MOSFET or an N-type FinFET.
Claims 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al., US 2019/0097006, in view of More et al., US 2019/0165124.
With respect to claim 12, Li et al. disclose a device, shown in Figs. 1 and 9, comprising:
a semiconductor substrate 200;
isolation regions 206 in the semiconductor substrate 200, as shown in Fig. 1;
a semiconductor fin 204;
a gate stack 256 over a top surface and sidewalls of the semiconductor fin 204, see Figs. 1 and 6; and
a source/drain region 220 aside of the semiconductor fin 204, wherein the source/drain region 220 comprises:
a first semiconductor layer 220-1 comprising a dopant having a first dopant concentration (5 x 1019 atoms/cm3, see paragraph [0028]);
a second semiconductor layer 220-2 over and contacting the first semiconductor layer 220-1,
wherein the second semiconductor layer comprises the dopant having a second dopant concentration (1 x 1020 atoms/cm3, see paragraph [0028]) higher than the first dopant concentration (5 x 1019 atoms/cm3, see paragraph [0028]), and
wherein the second semiconductor layer has an upper portion higher than the top surface of the semiconductor fin 204, and a lower portion lower than the top surface of the semiconductor fin 204, as shown in Fig. 9; and
a third semiconductor layer 220-3 over the second semiconductor layer 220-2, wherein the third semiconductor layer 220-3 comprises the dopant having a third dopant concentration (5 x 1019 atoms/cm3, see paragraph [0035]) lower than the second dopant concentration (1 x 1020 atoms/cm3, see paragraph [0028]). However, as shown in Figs. 1 and 6, Li et al. fail to teach or suggest the semiconductor fin 204 is higher than top surfaces of the isolation regions 206. In the same field of endeavor, More et al. disclose that in the step of forming recesses into fins 103 prior to epitaxially growing the Source/drain regions 104, the semiconductor fins 103 can be higher than top surfaces of the isolation regions 105, as shown in Figs. 1B and 2B of More et al. Therefore, in light of the disclosure of More et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the fin 204 in the known device of Li et al. could have been higher than top surfaces of the isolation regions 206, since it is known that epitaxial source/drain regions can be grown on fins either higher or lower than the top surfaces of isolation regions. In light of the disclosure of More et al., it would have been obvious to the skilled artisan to try epitaxially growing the source/drain regions 220 in the known device of Li et al. on a semiconductor fin 204 that is higher than top surfaces of the isolation regions 206. It has been well established that “obvious to try” is an acceptable rationale for supporting a conclusion of obviousness. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)
With respect to claim 13, the device of Li et al. further comprises a gate spacer 218 contacting the gate stack 256 and comprising a first sidewall. Although Fig. 1 of Li et al. does not expressly show the upper portion of the second semiconductor layer 220-2 comprises a second sidewall contacting the first sidewall to form a vertical interface, Fig. 1 clearly shows the source/drain region 220 forming a vertical interface with gate dielectric 252. Since gate spacer 218 is formed on gate dielectric layer 252, as shown in Fig. 9, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the source/drain region 220, including the second semiconductor layer 220-2, would form a vertical interface with gate spacer 218 with respect to what is shown in the simplified example of the FinFET of Li et al. shown in Fig. 1. Hence, since source/drain region 220 forms a vertical interface with gate spacer 218, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the upper portion of the second semiconductor layer 220-2 would comprise a second sidewall contacting the first sidewall to form a vertical interface, since the second semiconductor layer 220-2 is part of source/drain region 220.
With respect to claim 14, in the device of Li et al., a bottom surface of the second semiconductor layer 220-2 is slanted, as shown in Fig. 9, and wherein in a cross-sectional view of the device, a topmost point of the bottom surface of the second semiconductor layer 220-2 joins to a top corner of the semiconductor fin 204, as shown in Fig. 9.
With respect to claim 15, the device of Li et al. further comprises a silicide layer 240 over and contacting the second semiconductor layer 220-2, as shown in Fig. 9, see paragraph [0057].
With respect to claim 16, the device of Li et al. further comprises a contact plug 242/244 over and contacting the silicide layer 240, wherein the contact plug 242/244 and the silicide layer 240 comprise parts in the third semiconductor layer
220-3, as shown in Fig. 9
With respect to claim 17, in the device of Li et al., the dopant is an n-type dopant (see paragraphs [0020] and [0021]), and wherein the third semiconductor layer further comprises germanium, see paragraph [0028]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that an n-type MOSFET would have source/drain regions comprising an n-type dopant.
Claims 2-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al., US 2019/0097006, in view of Sung et al., US 2015/0021696.
With respect to claim 2, Li et al. disclose a device, shown in Figs. 1 and 9, comprising:
a semiconductor fin 204;
a gate stack 256 over a top surface and sidewalls of the semiconductor fin 204, see Figs. 1 and 9;
a gate spacer 218 on a sidewall of the gate stack 256, as shown in Fig. 9;
a source/drain region 220 aside of the gate spacer 218, as shown in Fig. 9 and comprising::
a first semiconductor layer 220-1 comprising a dopant in a first dopant concentration (5 x 1019 atoms/cm3, see paragraph [0028]);
a second semiconductor layer 220-2 over the first semiconductor layer 220-1,
wherein the second semiconductor layer comprises the dopant in a second dopant concentration (1 x 1020 atoms/cm3, see paragraph [0028]) higher than the first dopant concentration (5 x 1019 atoms/cm3, see paragraph [0028]), and
the second semiconductor layer comprises:
an upper portion contacting the gate spacer 218 to form a vertical interface (Since gate spacer 218 is formed on gate dielectric layer 252, as shown in Fig. 9, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the source/drain region 220, including the second semiconductor layer 220-2, would form a vertical interface with gate spacer 218 with respect to what is shown in the simplified example of the FinFET of Li et al. shown in Fig. 1. Hence, since source/drain region 220 forms a vertical interface with gate spacer 218, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second semiconductor layer 220-2 would also form a vertical interface with gate spacer 218, since the second semiconductor layer 220-2 is part of 220.), and
a lower portion lower than a top corner of the semiconductor fin 204, as shown in Fig. 9; and
a third semiconductor layer 220-3 over the second semiconductor layer 220-2, wherein the third semiconductor layer 220-3 comprises the dopant and has a third dopant concentration (5 x 1019 atoms/cm3, see paragraph [0035]) lower than the second dopant concentration (1 x 1020 atoms/cm3, see paragraph [0028]). However, Li et al. fail to anticipate the dopant is phosphorus. In the device of Li et al., the dopant is boron, see paragraphs [0028] and [0035]. However, in paragraphs [0020] and [0021], Li et al. disclose that the fabricated device can be an N-type MOSFET or an N-type FinFET. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the dopant used in the known device of Li et al. could have been phosphorus in order to fabricate an N-type MOSFET or an N-type FinFET, since phosphorus is a well-known n-type dopant, as taught by Sung et al. in paragraph [0011]..
With respect to claims 3-5, in the device of Li et al., a first topmost tip of a first top portion of the first semiconductor layer 220-1 is joined to the top corner of the semiconductor fin 204, as shown in Fig. 9. However, Li et al. does disclose that one of a top surface and a bottom surface of the first semiconductor layer 220-1 is on a (111) lattice plane of the first semiconductor layer 220-1. However, in the same field of endeavor, Sung et al. disclose openings 36, shown in Fig. 3, can include (11) planes, see paragraph [0014] of Sung et al. In light of the disclosure of Sung et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that openings in which the epitaxial source/drain regions are grown in the device of Li et al. could include a (111) lattice plane, since the openings of both Li and Sung have the same shape. Consequently, both the top surface and the bottom surface of the first semiconductor layer 220-1 is on the (111) lattice plane in the known device of Li et al.
With respect to claim 6, in the device of Li et al. in view of Sung et al., the second semiconductor layer 220-2 would have a highest phosphorous concentration in the source/drain region 220, see paragraphs [0028] and [0035] of Li et al..
With respect to claim 7, in the device of Li et al. in view of Sung et al., the third semiconductor layer 220-3 would comprise silicon, germanium, and phosphorous, see paragraph [0035] of Li et al.
With respect to claim 8, the device of Li et al. further comprises a silicide layer 240 and a contact plug 242/244 over and contacting the silicide layer 240, as shown in Fig. 9, wherein the silicide layer 240 and the contact plug 242/244 collectively penetrate through the third semiconductor layer 220-3, and the silicide layer 240 is over and contacting the second semiconductor layer 220-2, as shown in Fig. 9 of Li et al.
With respect to claim 9, in the device of Li et al., the silicide layer 240 physically contacts an edge of the third semiconductor layer 220-3, as shown in Fig. 9 of Li et al..
With respect to claim 11, the device of Li et al. further comprises a first semiconductor strip 204; and a second semiconductor strip 204 separated from the first semiconductor strip, as shown in Fig. 2B, wherein the first semiconductor layer 220-1 comprises: a first portion and a second portion overlapping the first semiconductor strip 204 and the second semiconductor strip 204, respectively; and a third portion joining the first portion to the second portion, as shown in Fi. 2B, see paragraph [0030]..
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al., US 2019/0097006, in view of Sung et al., US 2015/0021696, as applied to claim 2 above, further in view of More et al., US 2019/0165124.
Li et al. and Sung et al. are applied as above. However, Neither Li et al. nor Sung et al. disclose a device further comprising fin spacers on opposing sides pf the fin. In the same field of endeavor, More et al. disclose fin spacers 107 on the sidewalls of fins 103, as shown in Fig. 1B of More et al. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that fin spacers could be formed on sidewalls of fins 204 in the known device of Li et al. in order to provide stability to the fin during and after the epitaxial source/drain region is grown atop the fin 204. Forming fin spacers in the device of Li et al. would result in
fin spacers on opposing sides of a bottom portion of the first semiconductor layer 220-1, wherein a bottom surface of the first semiconductor layer 220-1 would be lower than top ends of the fin spacers, see Fig. 4B or Li et al. and Figs. 1B and 2B of More et al., and a top surface of the first semiconductor layer 220-1 would be higher than the top ends of the fin spacers, see Fig. 4B or Li et al. and Figs. 1B and 2B of More et al.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-9 and 12-21 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 18/365,996 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of both applications are drawn to semiconductor device in which the source/drain regions comprises a plurality of semiconductor layers. Independent claim 1 of the instant application is broader in scope than independent claim 1 of the reference application, and the claims of the instant application clearly encompass the semiconductor devices of the reference application, since independent claims 9 and 18 of the reference application do not require three semiconductor layers.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose semiconductor devices having epitaxially grown source/drain regions.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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