DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/24/2024, 2/3/2026 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 and 8 of U.S. Patent No. 11,810,961 in view of Yang (US 2020/0395489).
Regarding claim 1, Pat '961 discloses, in claim 1, a device comprising:
a gate dielectric over the channel region; and a gate electrode over the gate dielectric, the gate electrode comprising: a first work function tuning layer, the first work function tuning layer comprising a tungsten-free material; a second work function tuning layer over the first work function tuning layer, the second work function tuning layer comprising a tungsten-containing material, the tungsten-containing material having a lower resistivity than the tungsten-free material; and a fill layer over the second work function tuning layer ("a first nanostructure; a second nanostructure; a gate dielectric layer wrapped around the first nanostructure and the second nanostructure; a tungsten-free work function tuning layer wrapped around the gate dielectric layer; a tungsten-containing work function tuning layer wrapped around the tungsten-free work function tuning layer, an area between the first nanostructure and the second nanostructure being completely filled by respective portions of the tungsten-containing work function tuning layer, the tungsten-free work function tuning layer, and the gate dielectric layer, a first material of the tungsten-containing work function tuning layer having a lower resistivity than a second material of the tungsten-free work function tuning layer; and a fill layer on the tungsten-containing work function tuning layer", in claim 1 of Pat '961, is interpreted as the same limitation).
Pat '961 does not explicitly disclose a p-type source/drain region; a channel region adjacent the p-type source/drain region.
Yang teaches, in at least figures 18-19 and related text, the device comprising a p-type source/drain region (160, [35], [83], [114]); a channel region (110/210, [114]) adjacent the p-type source/drain region (160, [35], [83], [114]), for the purpose of providing multibridge-channel field-effect transistor (MBCFET) including a nanowire-type or nanosheet-type channel region ([32]) thereby improving density of integration.
Pat '961 and Yang are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '961 with the specified features of Yang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '961 to have the p-type source/drain region; the channel region adjacent the p-type source/drain region, as taught by Yang, for the purpose of providing multibridge-channel field-effect transistor (MBCFET) including a nanowire-type or nanosheet-type channel region ([32], Yang) thereby improving density of integration.
Regarding claim 2, Pat '961 in view of Yang discloses the device of claim 1 as described above.
Pat '961 further discloses, in claim 2, the tungsten-containing material is pure tungsten ("the tungsten-containing work function tuning layer comprises fluorine-free tungsten", in claim 2 of Pat '961, is interpreted as the same limitation).
Regarding claim 3, Pat '961 in view of Yang discloses the device of claim 1 as described above.
Pat '961 further discloses, in claim 3, the tungsten-containing material is a nitride or a carbide of tungsten ("the tungsten-containing work function tuning layer comprises tungsten nitride, tungsten carbide, or tungsten carbonitride", in claim 3 of Pat '961, is interpreted as the same limitation).
Regarding claim 4, Pat '961 in view of Yang discloses the device of claim 1 as described above.
Pat '961 further discloses, in claim 8, the tungsten-free material is a nitride of titanium or tantalum ("the tungsten-free work function tuning layer comprises titanium nitride", in claim 8 of Pat '961, is interpreted as the same limitation).
Regarding claim 5, Pat '961 in view of Yang discloses the device of claim 1 as described above.
Yang further teaches, in at least figures 18-19, 32-34, and related text, the channel region (110/210, [114]) is part of a first fin (F1, [149]), for the purpose of providing multibridge-channel field-effect transistor (MBCFET) including a nanowire-type or nanosheet-type channel region ([32]) thereby improving density of integration.
Regarding claim 6, Pat '961 in view of Yang discloses the device of claim 1 as described above.
Yang further teaches, in at least figures 18-19, 32-34, and related text, the channel region (110/210, [32], [114]) is part of a first nanostructure (110, [32], [114]) adjacent the p-type source/drain region (160, [35], [83], [114]), for the purpose of providing multibridge-channel field-effect transistor (MBCFET) including a nanowire-type or nanosheet-type channel region ([32]) thereby improving density of integration.
Regarding claim 7, Pat '961 in view of Yang discloses the device of claim 6 as described above.
Yang further teaches, in at least figures 18-19, 32-34, and related text, a second nanostructure (210, [32], [114]) adjacent the p-type source/drain region (160, [35], [83], [114]), the second nanostructure (210, [32], [114]) disposed above the first nanostructure (110, [32], [114]), wherein a first portion of the second work function tuning layer (144, [65]) is wrapped around the first nanostructure (110, [32], [114]), a second portion of the second work function tuning layer (144, [65]) is wrapped around the second nanostructure (210, [32], [114]), and the first portion of the second work function tuning layer (144, [65]) contacts the second portion of the second work function tuning layer (144, [65]) in an area between the first nanostructure (110, [32], [114]) and the second nanostructure (210, [32], [114]) (figures), for the purpose of providing multibridge-channel field-effect transistor (MBCFET) including a nanowire-type or nanosheet-type channel region ([32]) thereby improving density of integration.
Claims 8-9 and 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 5 and 8-10 of U.S. Patent No. 12,142,659. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 8, Pat '659 discloses, in claims 8-9, a device comprising:
a first transistor comprising: a first source/drain region; a first channel region adjacent the first source/drain region; a first gate dielectric over the first channel region; and a first gate electrode over the first gate dielectric, the first gate electrode comprising a first work function tuning layer, the first work function tuning layer comprising a tungsten-containing material; and a second transistor comprising: a second source/drain region, a first conductivity type of the first source/drain region being opposite from a second conductivity type of the second source/drain region; a second channel region adjacent the second source/drain region; a second gate dielectric over the second channel region; and a second gate electrode over the second gate dielectric, the second gate electrode comprising a second work function tuning layer, the second work function tuning layer comprising a first tungsten-free material ("a device comprising: a first transistor comprising: a first channel region; a first gate dielectric over the first channel region; and a first gate electrode over the first gate dielectric, the first gate electrode comprising a first work function tuning layer, the first work function tuning layer comprising a tungsten- containing material; and a second transistor comprising: a second channel region; a second gate dielectric over the second channel region; and a second gate electrode over the second gate dielectric, the second gate electrode comprising a second work function tuning layer, the second work function tuning layer comprising a tungsten-free material, the tungsten-free material having a higher resistivity than the tungsten-containing material" and “the first transistor further comprises a p-type source/drain region adjacent the first channel region, and the second transistor further comprises an n-type source/drain region adjacent the second channel region”, in claims 8 and 9 of Pat '659, are interpreted as the same limitation).
Regarding claim 9, Pat '659 discloses the device of claim 8 as described above.
Pat '659 further discloses, in claim 10, the first tungsten-free material is an aluminum-containing material ("the tungsten-free material is titanium aluminum", in claim 10 of Pat '659, is interpreted as the same limitation).
Regarding claim 12, Pat '659 discloses the device of claim 8 as described above.
Pat '659 does not explicitly disclose the first work function tuning layer is one of a plurality of work function tuning layers of the first gate electrode, each of the work function tuning layers comprising a tungsten-containing material.
Pat '659 teaches, in claim 5, the first work function tuning layer is one of a plurality of work function tuning layers of the first gate electrode, each of the work function tuning layers comprising a tungsten-containing material ("the second work function tuning layer comprises: a first layer of the first tungsten-containing material wrapped around the first work function tuning layer; and a second layer of a second tungsten-containing material wrapped around the first layer of the first tungsten-containing material, the second tungsten-containing material different from the first tungsten-containing material", in claim 5 of Pat '659, is interpreted as the same limitation), for the purpose of providing p-type devices with work function tuning layers formed of a tungsten-containing WFM having a lower resistance than p-type devices with work function tuning layers formed of a WFM that contains other metals (such as tantalum) thereby improving device performance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claims 8-9 of Pat '659 to have the first work function tuning layer being one of a plurality of work function tuning layers of the first gate electrode, each of the work function tuning layers comprising a tungsten-containing material, as taught by claim 5 of Pat '659, for the purpose of providing p-type devices with work function tuning layers formed of a tungsten-containing WFM having a lower resistance than p-type devices with work function tuning layers formed of a WFM that contains other metals (such as tantalum) thereby improving device performance.
Claims 10-11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8-9 of U.S. Patent No. 12,142,659 in view of claims 1 and 7-8 of U.S. Patent No. 11,810,961.
Regarding claim 10, Pat '659 discloses the device of claim 8 as described above.
Pat '659 does not explicitly disclose the first gate electrode further comprises a third work function tuning layer under the first work function tuning layer, the third work function tuning layer being thinner than the first work function tuning layer.
Pat '961 teaches, in claims 1 and 7, the first work function tuning layer is one of a plurality of work function tuning layers of the first gate electrode, each of the work function tuning layers comprising a tungsten-containing material ("a tungsten-containing work function tuning layer wrapped around the tungsten-free work function tuning layer" and “the tungsten-free work function tuning layer is thinner than the tungsten-containing work function tuning layer”, in claims 1 and 7 of Pat '961, are interpreted as the same limitation), for the purpose of providing p-type devices with work function tuning layers formed of a tungsten-containing WFM having a lower resistance than p-type devices with work function tuning layers formed of a WFM that contains other metals (such as tantalum) thereby improving device performance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '659 to have the first gate electrode further comprising a third work function tuning layer under the first work function tuning layer, the third work function tuning layer being thinner than the first work function tuning layer, as taught by Pat '961, for the purpose of providing p-type devices with work function tuning layers formed of a tungsten-containing WFM having a lower resistance than p-type devices with work function tuning layers formed of a WFM that contains other metals (such as tantalum) thereby improving device performance.
Regarding claim 11, Pat '659 discloses the device of claim 10 as described above.
Pat '961 further teaches, in claims 1 and 7-9, the third work function tuning layer comprises a second tungsten-free material, and wherein a resistivity of the first tungsten-free material is between a resistivity of the tungsten-containing material and a resistivity of the second tungsten-free material ("a tungsten-containing work function tuning layer wrapped around the tungsten-free work function tuning layer", “the tungsten-free work function tuning layer is thinner than the tungsten-containing work function tuning layer”, “the tungsten-containing work function tuning layer comprises fluorine-free tungsten or tungsten nitride, and the tungsten-free work function tuning layer comprises titanium nitride”, and “the tungsten-free work function tuning layer comprising titanium aluminum”, in claims 1 and 7-9 of Pat '961, are interpreted as the same limitation), for the purpose of providing p-type devices with work function tuning layers formed of a tungsten-containing WFM having a lower resistance than p-type devices with work function tuning layers formed of a WFM that contains other metals (such as tantalum) thereby improving device performance.
Claims 13-16 and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 5-7, 12-14 and 17 of U.S. Patent No. 12,142,659 in view of Yang (US 2020/0395489).
Regarding claim 13, Pat '659 discloses, in claims 12 and 17, a method comprising:
growing a p-type source/drain region adjacent to a first nanostructure; forming a gate dielectric layer around the first nanostructure and the second nanostructure; depositing a first tungsten-containing work function material over the gate dielectric layer until the first tungsten-containing work function material merges together in a region between the first nanostructure and the second nanostructure; and depositing a fill layer over the first tungsten-containing work function material ("forming a gate dielectric layer having a first portion wrapped around a first nanostructure and having a second portion wrapped around a second nanostructure; depositing a tungsten-containing work function material over the first portion of the gate dielectric layer; depositing a first tungsten-free work function material over the second portion of the gate dielectric layer, the first tungsten-free work function material having a higher resistivity than the tungsten-containing work function material; and depositing a fill layer over the first tungsten-free work function material and the tungsten-containing work function material” and “growing a p-type source/drain region adjacent the first nanostructure”, in claims 12 and 17 of Pat '659, are interpreted as the same limitation).
Pat '659 does not explicitly disclose a p-type source/drain region adjacent to adjacent to a second nanostructure; the first tungsten-containing work function material merges together in a region between the first nanostructure and the second nanostructure.
Yang teaches, in at least figures 18-19, 32-34, and related text, the method comprising a p-type source/drain region (160, [35], [83], [114]) adjacent to adjacent to a second nanostructure (210, [32], [114]); the first tungsten-containing work function material (144, [65]) merges together in a region between the first nanostructure (110, [32], [114]) and the second nanostructure (210, [32], [114]) (figures), for the purpose of providing multibridge-channel field-effect transistor (MBCFET) including a nanowire-type or nanosheet-type channel region ([32]) thereby improving density of integration.
Pat '659 and Yang are analogous art because they are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '659 with the specified features of Yang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '659 to have the p-type source/drain region; the channel region adjacent the p-type source/drain region, as taught by Yang, for the purpose of providing multibridge-channel field-effect transistor (MBCFET) including a nanowire-type or nanosheet-type channel region ([32], Yang) thereby improving density of integration.
Regarding claim 14, Pat '659 in view of Yang discloses the method of claim 13 as described above.
Pat '659 further discloses, in claim 13, depositing the first tungsten-containing work function material comprises: depositing fluorine-free tungsten by an ALD process, the ALD process performed with tungsten(V) chloride and hydrogen ("depositing the tungsten-containing work function material comprises: depositing fluorine-free tungsten by an ALD process, the ALD process performed with tungsten(V) chloride and hydrogen", in claim 13 of Pat '659, is interpreted as the same limitation).
Regarding claim 15, Pat '659 in view of Yang discloses the method of claim 13 as described above.
Pat '659 further discloses, in claim 14, depositing the first tungsten-containing work function material comprises: depositing tungsten nitride by an ALD process, the ALD process performed with bis(tert-butylimino)-bis-(dimethylamido)tungsten and ammonia ("depositing the tungsten-containing work function material comprises:depositing tungsten nitride by an ALD process, the ALD process performed with bis(tert- butylimino)-bis-(dimethylamido)tungsten and ammonia", in claim 14 of Pat '659, is interpreted as the same limitation).
Regarding claim 16, Pat '659 in view of Yang discloses the method of claim 13 as described above.
Yang further teaches, in at least figures 18-19, 32-34, and related text, depositing a tungsten-free work function material (144, [65]) over the gate dielectric layer (130, [56]), the first tungsten-containing work function material (144, [65]) being deposited over the tungsten-free work function material (142, [60]) (figures), for the purpose of providing multibridge-channel field-effect transistor (MBCFET) including a nanowire-type or nanosheet-type channel region ([32]) thereby improving density of integration.
Regarding claim 18, Pat '659 in view of Yang discloses the method of claim 13 as described above.
Pat '659 does not explicitly disclose depositing a second tungsten-containing work function material over the first tungsten-containing work function material, the second tungsten-containing work function material being different from first tungsten-containing work function material.
Pat '659 teaches, in claim 5, depositing a second tungsten-containing work function material over the first tungsten-containing work function material, the second tungsten-containing work function material being different from first tungsten-containing work function material ("the second work function tuning layer comprises: a first layer of the first tungsten-containing material wrapped around the first work function tuning layer; and a second layer of a second tungsten-containing material wrapped around the first layer of the first tungsten-containing material, the second tungsten-containing material different from the first tungsten-containing material”, in claim 5 of Pat '961, is interpreted as the same limitation), for the purpose of providing p-type devices with work function tuning layers formed of a tungsten-containing WFM having a lower resistance than p-type devices with work function tuning layers formed of a WFM that contains other metals (such as tantalum) thereby improving device performance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in claims 12 and 17 of Pat '659 to have the depositing a second tungsten-containing work function material over the first tungsten-containing work function material, the second tungsten-containing work function material being different from first tungsten-containing work function material, as taught by claim 5 of Pat '659, for the purpose of providing p-type devices with work function tuning layers formed of a tungsten-containing WFM having a lower resistance than p-type devices with work function tuning layers formed of a WFM that contains other metals (such as tantalum) thereby improving device performance.
Regarding claim 19, Pat '659 in view of Yang discloses the method of claim 18 as described above.
Pat '659 further teaches, in claim 7, depositing a third tungsten-containing work function material over the second tungsten-containing work function material, the third tungsten-containing work function material being different from the first tungsten-containing work function material ("the second work function tuning layer further comprises: a third layer of a third tungsten-containing material over the second layer of the second tungsten-containing material, the third tungsten-containing material different from the first tungsten-containing material”, in claim 7 of Pat '961, is interpreted as the same limitation), for the purpose of providing p-type devices with work function tuning layers formed of a tungsten-containing WFM having a lower resistance than p-type devices with work function tuning layers formed of a WFM that contains other metals (such as tantalum) thereby improving device performance.
Regarding claim 20, Pat '659 in view of Yang discloses the method of claim 18 as described above.
Pat '659 further teaches, in claim 6, depositing more of the first tungsten-containing work function material over the second tungsten-containing work function material ("the second work function tuning layer further comprises: a third layer of the first tungsten-containing material over the second layer of the second tungsten-containing material”, in claim 6 of Pat '961, is interpreted as the same limitation), for the purpose of providing p-type devices with work function tuning layers formed of a tungsten-containing WFM having a lower resistance than p-type devices with work function tuning layers formed of a WFM that contains other metals (such as tantalum) thereby improving device performance.
Claim 17 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 12 and 17 of U.S. Patent No. 12,142,659 in view of Yang (US 2020/0395489), and further in view of Lavric (US 2019/0305102).
Regarding claim 17, Pat '659 in view of Yang discloses the method of claim 13 as described above.
Pat '659 in view of Yang does not explicitly disclose the first tungsten-containing work function material is directly deposited on the gate dielectric layer.
Lavric teaches, in at least figure 2A and related text, the method comprising the first tungsten-containing work function material (255b, [28]) is directly deposited on the gate dielectric layer (255a, [28]), for the purpose of providing CMOS devices that include PMOS metal gates with a low threshold voltage ([14]).
Pat '659, Yang, and Lavric are analogous art because they are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '659 in view of Yang with the specified features of Lavric because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '659 in view of Yang to have the first tungsten-containing work function material being directly deposited on the gate dielectric layer, as taught by Lavric, for the purpose of providing CMOS devices that include PMOS metal gates with a low threshold voltage ([14], Lavric).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13 and 16 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yang (US 2020/0395489).
Regarding claim 13, Yang discloses, in at least figures 18-19, 25-39, and related text, a method comprising:
growing a p-type source/drain region (160, [35], [83], [114]) adjacent to a first nanostructure (110, [32], [114]) and adjacent to a second nanostructure (210, [32], [114]);
forming a gate dielectric layer (130, [51]) around the first nanostructure (110, [32], [114]) and the second nanostructure (210, [32], [114]);
depositing a first tungsten-containing work function material (144, [65]) over the gate dielectric layer (130, [51]) until the first tungsten-containing work function material (144, [65]) merges together in a region between the first nanostructure (110, [32], [114]) and the second nanostructure (210, [32], [114]); and
depositing a fill layer (148, [73]) over the first tungsten-containing work function material (144, [65]).
Regarding claim 16, Yang discloses the method of claim 13 as described above.
Yang further discloses, in at least figures 18-19, 25-39, and related text, depositing a tungsten-free work function material (144, [65]) over the gate dielectric layer (130, [51]), the first tungsten-containing work function material (144, [65]) being deposited over the tungsten-free work function material (142, [60]) (figures).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2020/0395489) in view of Lavric (US 2019/0305102).
Regarding claim 17, Yang discloses the method of claim 13 as described above.
Yang does not explicitly disclose the first tungsten-containing work function material is directly deposited on the gate dielectric layer.
Lavric teaches, in at least figure 2A and related text, the method comprising the first tungsten-containing work function material (255b, [28]) is directly deposited on the gate dielectric layer (255a, [28]), for the purpose of providing CMOS devices that include PMOS metal gates with a low threshold voltage ([14]).
Yang and Lavric are analogous art because they are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yang with the specified features of Lavric because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Yang to have the first tungsten-containing work function material being directly deposited on the gate dielectric layer, as taught by Lavric, for the purpose of providing CMOS devices that include PMOS metal gates with a low threshold voltage ([14], Lavric).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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