DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 7/24/24, 1/21/26, and 7/10/26 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 12 is objected to because of the following informalities:
Claim 12 recites “the sawing the reconstructed wafer and the device wafer” in lines 1 and 2., the examiner suggests “the sawing of the reconstructed wafer and the device wafer into a plurality of packages” for proper clarity and antecedence.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 2, 3, 4, 7, 8, 10, 11, 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) in view of Hung (US 2013/0062760)
Regarding claim 2.
Yu teaches:
A method comprising: attaching a first plurality of device dies (fig 13-15:261; [para 0060]) on a first carrier (fig 13-15:205; [para 0056]), wherein the first carrier (fig 13-15:205,210; [para 0056]) comprises a blank silicon layer (fig 13:205; [para 0033]) and a surface layer (fig 15:210; [para 0057]) over the blank silicon layer (fig 13:205; [para 0033]);
forming gap-filling regions (fig 14,15:257; [para 0060]) between the first plurality of device dies (fig 13-15:261; [para 0060]) to form a reconstructed wafer (fig 15);
attaching the reconstructed wafer to a second carrier (fig 25:206; [para 0080]);
de-bonding the reconstructed wafer from the first carrier (Fig 25,26:205; [para 0081]);
and sawing the reconstructed wafer into a plurality of packages (fig 27:102a,102b; [para 0083,0050]).
Yu does not teach attaching and thinning a semiconductor substrate
Hung teaches:
bonding a device wafer (fig 11:240; [para 0033]) to the recon structured wafer (fig 13:204,206; [para 0034]), wherein the device wafer (fig 11:240; [para 0033]) comprises: a first semiconductor substrate (fig 11:241; [para 0032]);
and a plurality of through-vias (fig 11:242; [para 0032]) in the first semiconductor substrate (fig 11:241; [para 0032]);
thinning the first semiconductor substrate (fig 16:241; [para 0036]) to reveal the plurality of through-vias (fig 11:242; [para 0036]);
forming electrical connectors (fig 17,19:210; [para 0036]) on the device wafer (fig 117,19:240; [para 0036]);
and cutting the reconstructed wafer (fig 19:204,206; [para 0038]) and the device wafer (fig 19:240; [para 0038]) into a plurality of packages (fig 19,20:260; [para 0038,0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach and thin a device wafer to the reconstructed wafer in order to facilitate device packaging and increase the density of circuitry and connection (paragraph 4).
Regarding claim 3.
Yu in view of Hung teaches the method of claim 2, further
Yu teaches:
wherein the first carrier (fig 13-15:205; [para 0056]) and the second carrier (fig 25:206; [para 0080]) contact opposing surfaces of the reconstructed wafer (fig 25; [para 0080]).
Regarding claim 4.
Yu in view of Hung teaches the method of claim 2, further
Yu teaches:
the attaching the first plurality of device dies (fig 13-15:261; [para 0060]) on the first carrier (fig 13-15:205; [para 0056]) comprising fusion bonding ([para 0057]).
Regarding claim 7.
Yu in view of Hung teaches the method of claim 2, further
Yu teaches:
front sides of the first plurality of device dies (fig 13-15:261; [para 0060]) are attached to the first carrier (fig 13-15:205,210; [para 0056]), and backsides of the plurality of device dies (fig 13-15:261; [para 0060]) face the second carrier (fig 25:206; [para 0080]).
Regarding claim 8.
Yu in view of Hung teaches the method of claim 7, further
Yu teaches:
the front sides of the first plurality of device dies (fig 13-15:261; [para 0060]) are revealed (fig 26; [para 0081]) after the reconstructed wafer is de-bonded from the first carrier (fig 13-15:205,210; [para 0056]).
Regarding claim 10.
Yu in view of Hung teaches the method of claim 2, further
Yu teaches:
the sawing (fig 26,27; [para 0083,0002]), removing the second carrier (fig 25:206; [para 0079])
Hung teaches:
before the singulation (fig 20; [para 0038]), removing the second carrier (fig 18,19:200; [para 0037]) from the reconstructed wafer (fig 18,19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to remove the carrier before sawing in order that there is less material to saw through thereby removing the time required for sawing.
Regarding claim 11.
Yu in view of Hung teaches the method of claim 10, further
Yu teaches:
before the reconstructed wafer (fig 15) is attached to the second carrier (fig 25:206; [para 0080]), forming a dielectric layer (fig 25:211; [para 0080]) on the reconstructed wafer, wherein the reconstructed wafer is attached to the second carrier (fig 25:206; [para 0080]) through the dielectric layer (fig 25:211; [para 0080]).
Regarding claim 12.
Yu in view of Hung teaches the method of claim 11, further
Yu teaches:
during the sawing the reconstructed wafer , the dielectric layer (fig 25:211; [para 0080]) is sawed (fig 26; [para 0083,0002]).
Hung teaches
the device wafer (fig 19:240; [para 0038])
Regarding claim 13.
Yu in view of Hung teaches the method of claim 11, further
Yu teaches:
the sawing the reconstructed wafer (fig 26; [para 0083,0002])
Hung teaches:
before the singulating the reconstructed wafer (fig 19,20; [para 0038]) and the device wafer (fig 19:240; [para 0038]), removing the dielectric layer (fig 18,19:202,250; [para 0037]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to remove the carrier before sawing in order that there is less material to saw through thereby removing the time required for sawing.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) in view of Hung (US 2013/0062760) as applied to claim 2 and further in view of Chen (US 2019/0355637).
Regarding claim 5.
Yu in view of Hung teaches the method of claim 2, above.
Yu in view of Hung does not teach the bonding comprises metal-to-metal bonding and fusion bonding.
Chen teaches:
the bonding the device wafer (fig 7g:615; [para 0054]) to the reconstructed wafer (fig 7f:7051-4; [para 0053]) comprises a bonding process comprises metal-to-metal bonding (fig 7g:611; [para 0054]) and fusion bonding (fig 7g:609; [para 0054]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a bonding process comprises metal-to-metal bonding and fusion bonding in order to remove the soldering step and allow for denser connections.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) in view of Hung (US 2013/0062760) as applied to claim 2 and further in view of Chen (US 2022/0093564).
Regarding claim 6.
Yu in view of Hung teaches the method of claim 2, above.
Yu in view of Hung does not teach forming a liner on the plurality of chips
Chen teaches:
forming the gap-filling regions (fig 8:L,M; [para 0081]) between the first plurality of device dies (fig 8:140,150; [para 0081]) comprises: depositing a dielectric liner (fig 8:L; [para 0081]) contacting the first plurality of device dies (fig 8:140,150; [para 0081]);
depositing a dielectric filling material (fig 8:M; [para 0081]) on the dielectric liner (fig 8:L; [para 0081]);
and performing a planarization process ([para 0081]) on the dielectric liner (fig 8:L; [para 0081]) and the dielectric filling material (fig 8:M; [para 0081]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a liner in the gap fill region in order to provide stress relief for the molding process (paragraph 81)
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) in view of Hung (US 2013/0062760) as applied to claim 2 and further in view of Kim (US 2013/0082399)
Regarding claim 9.
Yu in view of Hung teaches the method of claim 2, Above.
Yu in view of Hung does not teach the device wafer comprises a second semiconductor substrate
Kim teaches:
the device wafer comprises a second plurality of device dies (fig 15h,j:2000; [para 0144,0149]), each comprising a second semiconductor substrate (fig 15h:2000; [para 0144,0149]), and wherein the second semiconductor substrates (fig 15h:2000w; [para 0144m0149]) of the second plurality of device dies (fig 15h,15j:2000; [para 0144,0149]) are joined together to form a continuous semiconductor substrate (fig 15h:2000w; [para 0144]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second semiconductor substrate in order to secure sufficient space in a subsequent semiconductor package separating process (paragraph 0145)
Claim(s) 14, 15, 16, 17, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) in view of Hung (US 2013/0062760)
Regarding claim 14.
Yu teaches:
A method comprising: forming gap-filling regions (fig 14,15:257; [para 0060]) to fill gaps between a plurality of chips (fig 13-15:261; [para 0060]) to form a reconstructed wafer (fig 15);
attaching the reconstructed wafer to a first carrier (fig 25:206; [para 0080]);
after the reconstructed wafer is attached to the first carrier (fig 25:206; [para 0080]), revealing front surfaces of the plurality of chips (fig 26:261; [para 0081]);
.
Yu does not teach attaching and thinning a semiconductor substrate
Hung teaches:
bonding a device wafer (fig 11:240; [para 0033]) to the front surfaces of the plurality of chips (fig 13:204; [para 0034]);
thinning a semiconductor substrate (fig 11:241; [para 0032]) of the device wafer (fig 11:240; [para 0033]) to reveal a plurality of through-vias (fig 11:242; [para 0036]) in the device wafer (fig 11:240; [para 0033]);
and forming a plurality of electrical connectors (fig 17,19:210; [para 0036]) electrically connecting to the plurality of through-vias (fig 11:242; [para 0036]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach and thin a device wafer to the reconstructed wafer in order to facilitate device packaging and increase the density of circuitry and connection (paragraph 4).
Regarding claim 15.
Yu in view of Hung teaches the method of claim 14, further:
Yu teaches:
the revealing the front surfaces of the plurality of chips (fig 25,26:261; [para 0060])comprises detaching a second carrier (fig 25,26:205,210; [para 0056]) from the front surfaces of the plurality of chips (fig 25,26:261; [para 0060]).
Regarding claim 16.
Yu in view of Hung teaches the method of claim 15, further:
Yu teaches:
before the forming the gap-filling regions (fig 12-15:257; [para 0060]), bonding the plurality of chips (fig 12-15:261; [para 0060]) to the second carrier (fig 12-15:205,210; [para 0056]).
Regarding claim 17.
Yu in view of Hung teaches the method of claim 15, further:
Yu teaches:
the first carrier (fig 25:206; [para 0080]) is bonded to the plurality of chips (fig 25,26:261; [para 0060]) through fusion bonding ([para 0080]).
Regarding claim 18.
Yu in view of Hung teaches the method of claim 15, further:
Yu teaches:
the gap-filling regions (fig 25:257; [para 0060]) are formed when the plurality of chips (fig 25:261; [para 0060]) are attached to the second carrier (fig 14,15,25,26:205,210; [para 0056]).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) in view of Hung (US 2013/0062760)
Regarding claim 19.
Yu teaches:
A method comprising: a plurality of chips in a reconstructed wafer (fig 15), wherein the reconstructed wafer (fig 15) comprises: the plurality of chips (fig 13-15:261; [para 0060]);
gap-filling regions (fig 14,15:257; [para 0060])surrounding the plurality of chips (fig 13-15:261; [para 0060]);
and a dielectric bond layer (fig 15,25:210; [para 0080]) contacting the gap-filling regions (fig 14,15:257; [para 0060]);
after the first wafer (fig 25:206; [para 0080]) is bonded to the plurality of chips (fig 25:261; [para 0060]), removing ([para 0083]) a first carrier (fig 25,26:206; [para 0081]) that is bonded to the plurality of chips (fig 25:261; [para 0060]);
;
and sawing the reconstructed wafer to form a plurality of packages (fig 27:102a,102b; [para 0083,0050]).
Yu does not teach attaching and thinning a semiconductor substrate
Hung teaches:
bonding a front side of a first wafer (fig 11:240; [para 0033]) to a plurality of chips (fig 13:204; [para 0034]);
thinning a semiconductor substrate (fig 16:241; [para 0036]) of the first wafer (fig 11:240; [para 0033]) to reveal a plurality of through-vias (fig 11:242; [para 0036]) in the first wafer (fig 11:240; [para 0033]);
forming a plurality of electrical connectors (fig 17,19:210; [para 0036]) on a backside of the first wafer (fig 11:240; [para 0033]), wherein the plurality of electrical connectors (fig 17,19:210; [para 0036]) are electrically connected to the plurality of chips (fig 13,17:204; [para 0034]) through the first wafer (fig 11:240; [para 0033]);
and cutting the first wafer (fig 11:240; [para 0033]) to form a plurality of packages (fig 19,20:260; [para 0038,0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach and thin a device wafer to the reconstructed wafer in order to facilitate device packaging and increase the density of circuitry and connection (paragraph 4).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) in view of Hung (US 2013/0062760) as applied to claim 19 and further in view of Kim (US 2013/0082399)
Regarding claim 20.
Yu in view of Hung teaches the method of claim 19, Above.
Yu in view of Hung does not teach a second wafer.
Kim teaches:
bonding a second wafer (fig 15H:2000w; [para 0143]) to the first wafer (fig 15h:200; [para 0143]), wherein the second wafer (fig 15H:2000w; [para 0143]) is sawed into the plurality of packages (fig 15j:10000d; [para 0149]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second semiconductor substrate in order to secure sufficient space in a subsequent semiconductor package separating process (paragraph 0145)
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) in view of Hung (US 2013/0062760) as applied to claim 19 and further in view of Chen (US 2022/0093564).
Regarding claim 21.
Yu in view of Hung teaches the method of claim 19, above.
Yu in view of Hung does not teach forming a liner on the plurality of chips
Chen teaches:
the gap-filling regions comprises a dielectric liner (fig 8:L; [para 0081]) and a dielectric filling material (fig 8:M; [para 0081]) on the dielectric liner (fig 8:L; [para 0081]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a liner in the gap fill region in order to provide stress relief for the molding process (paragraph 81).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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