DETAILED ACTION
This Office action is in response to the filing of this application on 24 July 2024. Claims 1-20 are pending in the application. Claims 1, 11, and16 are independent.
This application is a continuation of application Serial No. 17/869,558, filed on 20 July 2022, pending, which is a divisional of application Serial No. 16/887,154, filed on 29 May 2020, now US Patent 11,935,793.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 6, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Dependent claims 5-6 and dependent claim 18 require the first impurities are arsenic antimony or carbon, and wherein the second impurities are phosphorus. Independent claims 1 and 16, from which claims 5-6 and 18 depend, respectively, require the first impurities to have a lower formation enthalpy than the second impurities. However, as evidenced by the “Standard Thermodynamic Properties of Chemical Substances”, phosphorus can have a lower formation enthalpy than arsenic. Hence, dependent claims 5-6 and 18 are confusing and/or incorrect. Since Applicant’s specification clearly teaches that arsenic has a lower formation enthalpy than a phosphorus dimer, see paragraph [0010] of the specification, claims 5-6 and 18 should be limited to the second impurity being a phosphorus dimer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 6, 7, and 8 rejected under 35 U.S.C. 103 as being unpatentable over
Roh et al., US 2018/0076326, cited by Applicant on the Information Disclosure Statement submitted on 24 July 2024, in light of “Standard Thermodynamic Properties of Chemical Substances” in CRC Handbook of Chemistry and Physics, 100th Edition (Internet Version 2019), John R. Rumble, ed., CRC Press/Taylor & Francis, Boca Raton, FL.
With respect to claim 1, Roh et al. disclose a method comprising:
etching a recess 115 in a semiconductor substrate 110, the recess 115 being adjacent to a gate stack 120/130, see Figs. 1B-1C and paragraph [0019];
forming a source/drain region 200/205/210 in the recess 115, wherein forming the source/drain region comprises:
epitaxially growing a first epitaxy material 205/210 in the recess 115;
performing a first implantation process 305 to implant first impurities (phosphorus) in the first epitaxy material 205/210;
performing a second implantation process 300 to implant second impurities (arsenic) in the first epitaxy material 205/210,
wherein the first impurities (phosphorus, formation enthalpy 58.9 kj/mole, see “Standard Thermodynamic Properties of Chemical Substances”) have a lower formation enthalpy than the second impurities (arsenic, formation enthalpy 302.5 kj/mole, see “Standard Thermodynamic Properties of Chemical Substances”), see Fig. 3 and paragraphs [0021]-[0023];
performing an annealing process after the first implantation process 305 and the second implantation process 300 to define:
a first doped region 205 comprising the first impurities (phosphorus); and
a second doped region 210 comprising the second impurities (arsenic), wherein the first impurities (phosphorus) of the first doped region 205 are disposed at a top surface of the semiconductor substrate 110 and extend along (interior) sides of the second doped region 210, as shown in Fig. 4, see paragraph [0024].
With respect to claim 7, in the method of Roh et al., the first impurities (phosphorus) of the first doped region 205 further extend below the second impurities (arsenic) of the second doped region 210, as shown in Fig. 4.
With respect to claim 8, as shown in Fig. 4, in the method of Roh et al., after the annealing process, wherein a concentration of the second impurities (arsenic) in the second doped region 210 increases in a direction towards a top surface of the first epitaxy material 205/210, since the concentration of arsenic in the second doped region 205 is less than the concentration of arsenic in the second doped region 210.
Alternately, with respect to claim 1, Roh et al. disclose a method comprising:
etching a recess 115 in a semiconductor substrate 110, the recess 115 being adjacent to a gate stack 120/130, see Figs. 1B-1C and paragraph [0019];
forming a source/drain region 200/205/210 in the recess 115, wherein forming the source/drain region comprises:
epitaxially growing a first epitaxy material 205/210 in the recess 115;
performing a first implantation process 300 to implant first impurities (arsenic) in the first epitaxy material 205/210;
performing a second implantation process 305 to implant second impurities (phosphorus) in the first epitaxy material 205/210,
wherein the first impurities (arsenic, formation enthalpy 302.5 kj/mole, see “Standard Thermodynamic Properties of Chemical Substances”) have a lower formation enthalpy than the second impurities (phosphorus, formation enthalpy 316.5 kj/mole, see “Standard Thermodynamic Properties of Chemical Substances”), see Fig. 3 and paragraphs [0021]-[0023];
performing an annealing process after the first implantation process 300 and the second implantation process 305 to define:
a first doped region 210 comprising the first impurities (arsenic); and
a second doped region 205 comprising the second impurities (phosphorus), wherein the first impurities (arsenic) of the first doped region 210 are disposed at a top surface of the semiconductor substrate 110 and extend along sides of the second doped region 205, as shown in Fig. 4, see paragraph [0024].
With respect to claim 5, in the method of Roh et al., the first impurities comprise arsenic, antimony or carbon, see paragraph [0022].
With respect to claim 6, in the method of Roh et al., 6. The method of claim 5, wherein the second impurities comprise phosphorus, see paragraph [0023].
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over
Roh et al., US 2018/0076326, in light of “Standard Thermodynamic Properties of Chemical Substances”, as applied to claim 1 above, further in view of Ma et al. 2020/0105934, cited by Applicant on the Information Disclosure Statement submitted on 24 July 2024.
Roh et al. is applied as above. With respect to claim 2, in the method of Roh et al., before epitaxially growing the first epitaxy material 205/210 in the recess 115, epitaxially growing a second epitaxy material 200 in the recess (see Fig. 2 and paragraph [0020]), wherein the first epitaxy material 205/210 is doped with third impurities (phosphorus) while epitaxially growing the first epitaxy material 205/210 (see paragraph [0021]). However, Roh et al. do not teach the second epitaxy material 200 is doped with fourth impurities while epitaxially growing the second epitaxy material. Rather, Roh et al. teach that the second epitaxy material 200 is undoped, see paragraph [0020]. However, in the same field of endeavor, Ma et al. disclose a method of forming epitaxial source/drain regions in which epitaxial layer 82A is in-situ doped with Ge, As, or P, see paragraph [0038]. In light of the teaching of Ma et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second epitaxy material 200 in the known method of Roh et al. could have been doped, since the prior art clearly teaches that the first eopitaxially layer formed in a source/drain recess can be either undoped or doped, and either results in the formation of source/drain regions of a transistor.
With respect to claim 3, Ma et al. disclose that the fourth dopants can be Ge or arsenic. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the fourth impurities can be a different element than the third impurities (phosphorus).
With respect to claim 4, in the method of Roh et al. in view of Ma et al., a concentration of the third impurities (phosphorus) in the first epitaxy material 205/210 is greater than a concentration of the fourth impurities (germanium) in the second epitaxy material 200.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Roh et al.,
US 2018/0076326, in light of “Standard Thermodynamic Properties of Chemical Substances”, as applied to claim 1 above, further in view of Noguchi et al., US 2012/0199896.
Roh et al. is applied as above. Roh et al. fail to disclose forming a source/drain contact extending into the second doped region 210, wherein a concentration of the second impurities at a bottom surface of the source/drain contact is at least 1023 cm-3. In the same field of endeavor, Noguchi et al. disclose a method of fabricating a transistor which comprises forming a contact 15 extending into a doped region 9 having a concentration of the impurities at a bottom surface of the source/drain contact 15 of 1023 cm-3, as shown in Fig. 5, see paragraph [0048]. In light of the teaching of Noguchi et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a source/drain contact extending into the second doped region 210 could have been formed in the known method of Roh et al.
Since Roh et al. teach that the second doped region 210 is highly doped (n++), as shown in Fig. 4, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (in light of Noguchi et al.) that a concentration of the impurities at a bottom surface of the source/drain contact could be at least 1023 cm-3.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Roh et al., US 2018/0076326, in light of “Standard Thermodynamic Properties of Chemical Substances”, as applied to claim 1 above, and further in view of Feng et al., US 2016/0190251, cited by Applicant on the Information Disclosure Statement submitted on 24 July 2024, and More et al., US 10,164,048.
Roh et al. is applied as above. Although Roh et al. disclose annealing the source/drain regions after ion implantation (see paragraph [0024]), Roh et al. lack anticipation of the annealing of the source/drain region comprising performing a microsecond anneal (µSSA) on the source/drain region; and after performing the microsecond anneal (µSSA), performing a laser spike anneal (LSA) on the source/drain region. Feng et al. disclose that after ion implantation of the source/drain regions of a finFET, a rapid thermal anneal and a laser spike anneal can be performed to activate the dopants and recrystallize the source/drain region, see paragraph [0033]. Feng et al. fail to disclose that the rapid thermal anneal is a microsecond anneal. However, More et al. disclose that to activate dopants in the source/drain regions of a finFET using one or more annealing processes, such as microsecond annealing, rapid thermal annealing, dynamic spike annealing, microwave annealing, or melting laser annealing, see column 10, lines 19-24. Given the disclosure of More et al., it would have been obvious to the skilled artisan that a microsecond annealing could have been substituted for the rapid thermal annealing step disclosed by Feng et al., since More et al. disclose that the two annealing techniques are functionally equivalent.
Claims 11, 12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., US 2008/0023752, in view of Roh et al., US 2018/0076326, both cited by Applicant on the Information Disclosure Statement submitted on 24 July 2024.
With respect to claim 11, Chen et al. disclose a method, shown in Figs. 1-7, comprising:
etching a recess 118 in a semiconductor substrate 102, the recess 118 being adjacent to a gate stack 100, as shown in Fig. 2;
epitaxially growing a first epitaxy material 232/234 in the recess 118, see paragraph [0017];
performing a first implantation process 239 to implant arsenic in the first epitaxy material 232/234 (Chen et al. disclose that an implant 239 is performed using an n-type dopant, such as phosphorous and arsenic after epitaxially growing layer 232/234.), see Fig. 4 and paragraph [0017];
performing a second implantation process 239 to implant phosphorus in the first epitaxy material 232/234 (Chen et al. disclose that an implant 239 is performed using an n-type dopant, such as phosphorous and arsenic after epitaxially growing layer 232/234.), see Fig. 4 and paragraph [0017];
after the second implantation process 239, performing an annealing process 154, wherein the annealing process defines:
a first doped region 156/232 comprising arsenic; and
a second doped region 152 comprising phosphorus, the second doped region 152 being at least partially disposed in the first epitaxy material 232/234, wherein arsenic of the first doped region 156/232 extend along sides of and below the second doped region 152, see Fig. 6 and paragraph [0018]. Chen et al. lack anticipation only of performing the second implantation process after the first implantation process. In the same field of endeavor, Roh et al. disclose a method comprising: epitaxially growing a first epitaxy material 205/210 in the recess 115; performing a first implantation process 300 to implant arsenic in the first epitaxy material 205/210; after the first implantation process 300, performing a second implantation process 305 to implant phosphorus in the first epitaxy material 205/210, see Fig. 3 and paragraphs [0022]-[0023]; and after the second implantation process, performing an annealing process (see paragraph [0024]). In light of the method of Roh et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the second implantation process to implant phosphorus after the first implantation process to implant arsenic in the known method of Chen et al..
With respect to claim 12, Chen et al. disclose forming gate spacers 112/140 along sidewalls of the gate stack 100, wherein annealing process 154 further diffuses phosphorus laterally under the gate spacers 112/140, as shown in Fig.6.
With respect to claim 15, in the method of Chen et al., there is no annealing process is performed between the first implantation process and the second implantation process.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Roh et al., as applied to claim 11 above, and further in view of Nieh et al., US 2008/0293204, cited by Applicant on the Information Disclosure Statement submitted on 24 July 2024.
Chen et al. and Roh et al. are applied as above. Although both Chen et al. and Roh et al. disclose the second implantation process comprises implanting phosphorous, neither Chen et al. or Roh et al. disclose the second implantation process comprises implanting phosphorous dimer in the first epitaxy material 232/234. Nieh et al. disclose that implanting phosphorous dimer reduces junction depth and improves short channel characteristics, see paragraph [0007]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second implantation process could comprise implanting phosphorous dimer in the first epitaxy material 232/234 in the known method of Chen et al. in order to reduce junction depth and improve short channel characteristics of the transistor.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Roh et al., further in view of Nieh et al., as applied to claim 13 above, in view of Noguchi et al., US 2012/0199896.
Chen et al., Roh et al., and Nieh et al. are applied as above. Neither Chen et al., Roh et al., or Nieh et al. disclose the second implantation process comprises using an implantation dosage in a range of 1018 cm-3 to 1022 cm-3. However, in the same field of endeavor, Noguchi et al. disclose a source/drain region can have a concentration of implanted n-type impurities greater than 1019 cm-3 to 1023 cm-3, see paragraph [0048]. In light of the teaching of Noguchi et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second implantation process could comprise using an implantation dosage in a range of 1018 cm-3 to 1022 cm-3. This limitation is not deemed to patentably distinguish Applicant’s claimed method from that of the applied prior art.
Claims 16, 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Roh et al., US 2018/0076326, in light of “Standard Thermodynamic Properties of Chemical Substances” in CRC Handbook of Chemistry and Physics, 100th Edition (Internet Version 2019), John R. Rumble, ed., CRC Press/Taylor & Francis, Boca Raton, FL, further in view of Noguchi et al., US 2012/0199896.
With respect to claim 16, Roh et al. disclose a method comprising:
forming a gate stack 120/130 at a top surface of a semiconductor substrate 110, as shown in Fig. 1B;
etching an opening 115 adjacent to a gate stack 120/130, see Figs. 1B-1C and paragraph [0019];
epitaxially growing a first epitaxy region 200/205/210 in the opening 115, wherein the first epitaxy region 205/210 is grown to a top surface of the semiconductor substrate 110, as shown in Fig. 2, see paragraph [0021];
sequentially implanting first impurities (phosphorus) and second impurities (arsenic) in the first epitaxy region 205/210, the first impurities (phosphorus, formation enthalpy 58.9 kj/mole, see “Standard Thermodynamic Properties of Chemical Substances”) having a lower formation enthalpy than the second impurities (arsenic, formation enthalpy 302.5 kj/mole, see “Standard Thermodynamic Properties of Chemical Substances”), see Fig. 3 and paragraphs [0022]-[0023];
performing an annealing process on the first epitaxy region 205/210 to form a first doped region 205 and a second doped region 210, see Fig. 4 and paragraph [0024],
the first doped region 205 being doped with the first impurities (phosphorus),
the second doped region 210 doped with the second impurities (arsenic),
the first impurities (phosphorus) of the first doped region 205 extending along sides of the second impurities (arsenic) of the second doped region 210 and below the second impurities (arsenic) of the second doped region 210, as shown in Fig. 4. Roh et al. lack anticipation only of forming a source/drain contact extending into the second doped region 210. In the same field of endeavor, Noguchi et al. disclose a method of fabricating a transistor which comprises forming a contact 15 extending into a doped region 9, as shown in Fig. 5. In light of the teaching of Noguchi et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a source/drain contact extending into the second doped region 210 in the known method of Roh et al., to complete fabrication of the transistor of Roh et al.
With respect to claim 17, although Roh et al. disclose that the second impurities (arsenic) in the second doped region 210 has a concentration of n++, Roh et al. do not specifically disclose that the concentration of the second at the source/drain contact is at least 1023 cm-3. However, Noguchi et al. disclose that the concentration of impurities at the source/drain contact 15 is 1023 cm-3, see paragraph [0048]. Therefore, since Roh et al. teach that the second doped region 210 is highly doped (n++), as shown in Fig. 4, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (in light of Noguchi et al.) that a concentration of the impurities at the source/drain contact could be at least 1023 cm-3.
With respect to claim 19, in the combination of Roh et al. and Noguchi et al., a concentration of the second impurities (arsenic) is highest at an interface between the source/drain contact and the second doped region 210, since the second doped region has the highest dopant concentration (n++).
With respect to claim 20, in the method of Roh et al., epitaxially growing the first epitaxy region 205/210 comprises epitaxially growing the first epitaxy region while doping the first epitaxy region 205/210 with third impurities, see paragraph {0021} (Epitaxial layer 210 is in-situ doped during the SEG deposition with an n-type dopant such as phosphorus.)
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 6, and 13-18 of U.S. Patent No. 11,935,793. Although the claims at issue are not identical, they are not patentably distinct from each other because the pending claims are broader in scope than the patented claims. Therefore, the patented claims clearly encompass the method of the pending claims
Conclusion
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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