DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-10 and 17-26 remain pending in this application. Acknowledgement is made of the amendment received 02/26/2025. Claims 11-16 are canceled, and claims 21-26 are added for consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7, 9 and 10 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 7, the claim recites the term “substantially”, which does not adequately define the metes and bounds of the claim, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. One of ordinary skill in the art would only conclude that certain exemplary embodiments qualify, but without a definite criterion by which to ascertain whether any non-disclosed embodiments so qualifies. For example, it is unclear if the claim is intended to limit an angle to vertical to a range of values, such as +/-5%, +/-10%, or some other range. This renders the scope of the claim indefinite. For the purpose of compact prosecution, the Examiner has interpreted the claim to mean “are aligned along a
Regarding claim 9, the claim recites the term “approximately 1.6 to approximately 1.9”, which does not adequately define the metes and bounds of the claim, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. One of ordinary skill in the art would only conclude that certain exemplary embodiments qualify, but without a definite criterion by which to ascertain whether any non-disclosed embodiments so qualifies. For example, it is unclear if the claim is intended to limit the refractive index to a certain range of values, such as +/-5%, +/-10%, or some other range. This renders the scope of the claim indefinite. For the purpose of compact prosecution, the Examiner has interpreted the claim to mean “a refractive index ranging from
Regarding claim 10, the claim recites the term “approximately 2000 angstroms”, which does not adequately define the metes and bounds of the claim, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. One of ordinary skill in the art would only conclude that certain exemplary embodiments qualify, but without a definite criterion by which to ascertain whether any non-disclosed embodiments so qualifies. For example, it is unclear if the claim is intended to limit the lower bound thickness to a range of values, such as +/-5%, +/-10%, or some other range. This renders the scope of the claim indefinite. For the purpose of compact prosecution, the Examiner has interpreted the claim to mean “greater than
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 20170110467 A1, as cited in the IDS dated 11/20/2025, hereafter Chen) in view of Seah et al (US 6689653 B1, as cited in the IDS dated 07/24/2024, hereafter Seah).
Regarding claim 1, Chen teaches: An integrated chip (IC)(Chen 2), comprising:
a substrate (Chen 100, ¶0038);
a floating gate electrode (Chen 14, FG, ¶0040) disposed over the substrate (Chen fig 2);
a contact etch stop layer (CESL) structure (Chen 312) disposed over the floating gate electrode (Chen fig 2, ¶0050);
an insulating stack (Chen 300, ¶0045, at least a stack of one layer, “silicon oxide”, applicant discloses suitable materials of an insulating stack include “silicon oxide”, spec ¶0025; see MPEP 2112.01) separating the floating gate electrode from the CESL structure (Chen fig 2, ¶0050, claim 5), the insulating stack comprising:
a first resist protective layer (Chen 300) disposed over the floating gate electrode (Chen fig 2, ¶0045);
Chen does not teach: the insulating stack comprising:
a second resist protective layer disposed over the first resist protective layer; and
an insulating layer separating the first resist protective layer from the second resist protective layer.
Seah, in the same field of endeavor of semiconductor device manufacturing, teaches: an insulating stack (Seah 11, ¶, comprising 8, 9b, and 10) comprising:
a first resist protective layer (Seah 8) disposed over a floating gate electrode (Seah 7)(Seah figs 3, 4);
a second resist protective layer (Seah 10) disposed over the first resist protective layer (Seah fig 3); and
an insulating layer (Seah 9b) separating the first resist protective layer from the second resist protective layer (Seah fig 3).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the insulating stack of Chen with the insulating stack of Seah to improve the data retention characteristics of non-volatile memory (Chen ¶0051, Seah col 1, lines 20-31).
Regarding claim 2, Chen in view of Seah teaches: The IC of claim 1, further comprising:
a select gate electrode (Chen 12, SG, ¶0039) disposed over the substrate (Chen 100)(Chen fig 2), wherein the CESL structure (Chen 312) separates the select gate electrode from the insulating stack (Chen 300 as modified by Seah 11) in a lateral direction (Chen fig 2).
Regarding claim 3, Chen in view of Seah teaches: The IC of claim 2, wherein the CESL structure (Chen 312) continuously extends over the floating gate electrode (Chen 14, FG) and the select gate electrode (Chen 12, SG)(Chen fig 2, ¶0050).
Regarding claim 4, Chen in view of Seah teaches: The IC of claim 1, wherein the first resist protective layer (Chen 300 as modified by Seah 11, similar to Seah 8) and the second resist protective layer (Chen 300 as modified to include Seah 10) comprise a first material (Chen ¶0045, “silicon oxide”, Seah col 3, line 60, “silicon dioxide layer 8”, col 4, line 14, “silicon oxide layer 10”), and wherein the insulating layer (Chen 300 as modified to include Seah 9b) comprises a second material (Seah col 4, line 8, “silicon nitride layer 9b”) different than the first material (silicon oxide being different from silicon oxide).
Regarding claim 6, Chen in view of Seah teaches: The IC of claim 1, wherein an outer sidewall of the second resist protective layer (Chen 300 as modified to include Seah 10) extends below the insulating layer (Chen 300 as modified to include Seah 9b)(Seah fig 3, an outer side wall of Seah 9b extends below at least a portion of the insulating layer).
Regarding claim 7, Chen in view of Seah teaches: The IC of claim 1, wherein an outer sidewall of the insulating layer (Chen 300 as modified to include Seah 9b) and an outer sidewall of the second resist protective layer (Chen 300 as modified to include Seah 10) are aligned along a substantially vertical axis (as best understood to mean “along a .
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 20170110467 A1, as cited in the IDS dated 11/20/2025, hereafter Chen) in view of Seah et al (US 6689653 B1, as cited in the IDS dated 07/24/2024, hereafter Seah), as applied to claim 1 above, and further in view of Li et al (US 20150091073 A1, as cited in the IDS dated 07/24/2024, hereafter Li).
Regarding claim 5, Chen in view of Seah teaches: The IC of claim 1.
Chen in view of Seah does not explicitly teach: a capacitor disposed between the substrate and the insulating stack, wherein a first portion of the substrate is separated from a second portion of the substrate by an isolation structure, wherein the floating gate electrode overlies the first portion of the substrate, wherein the capacitor overlies the second portion of the substrate, and wherein the floating gate electrode is connected to the capacitor by a coupling segment that continuously extends over the isolation structure.
Li, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: a capacitor (Li “extending device”, ¶0043, “an N-type MOS capacitor, or a P-type MOS capacitor”) disposed between a substrate (Li 100, ¶0024) and an insulating stack (Li 300, 312, ¶0031), wherein a first portion of the substrate (Li 101, ¶0024, 0034) is separated from a second portion (Li 101’, ¶0043) of the substrate by an isolation structure (Li 102, ¶0024, 0034), wherein a floating gate electrode (Li 14, ¶0025) overlies the first portion of the substrate (Li fig 8, ¶0025), wherein the capacitor overlies the second portion of the substrate (Li fig 8, ¶0043), and wherein the floating gate electrode is connected to the capacitor by a coupling segment that continuously extends over the isolation structure (Li fig 3, 8, ¶0034, 0043, 14 continuously extends across 101, 101’, 101’’ in the y dir, 102 extends in the x dir therebetween).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the IC of Chen in view of Seah such that it comprises “a capacitor disposed between the substrate and the insulating stack, wherein a first portion of the substrate is separated from a second portion of the substrate by an isolation structure, wherein the floating gate electrode overlies the first portion of the substrate, wherein the capacitor overlies the second portion of the substrate, and wherein the floating gate electrode is connected to the capacitor by a coupling segment that continuously extends over the isolation structure”, as taught by Li, in order to provide capacitive coupling between a floating gate, control gate, and erase gates, thereby improving charge retention performance of the device (Li ¶0043).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 20170110467 A1, as cited in the IDS dated 11/20/2025, hereafter Chen) in view of Seah et al (US 6689653 B1, as cited in the IDS dated 07/24/2024, hereafter Seah), as applied to claim 1 above, and further in view of Bu et al (US 20110215419 A1, hereafter Bu).
Regarding claim 8, Chen in view of Seah teaches: The IC of claim 1, wherein the CESL structure (Chen 312) has a first thickness (Chen fig 1, Seah fig 3) and the insulating stack (Chen 300 as modified by Seah 11) has a second thickness (Chen fig 1, Seah fig 3).
Chen in vies of Seah does not explicitly teach: wherein the first thickness is less than the second thickness.
Bu, in the same field of endeavor of semiconductor device manufacturing, teaches: a CESL structure (Bu 130, ¶0009, 0034) has a first thickness (Bu ¶0034) and an insulating stack (Bu 120, ¶0006) has a second thickness (Bu ¶0013), wherein the first thickness is less than the second thickness (Bu ¶0013, 0017).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust the thickness of the CESL or the insulating such that “the first thickness is less than the second thickness”, as taught by Bu, in order to reduce the rate of charge leakage from the floating gate electrode (Bu ¶0013).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 20170110467 A1, as cited in the IDS dated 11/20/2025, hereafter Chen) in view of Seah et al (US 6689653 B1, as cited in the IDS dated 07/24/2024, hereafter Seah), as applied to claim 1 above, and further in view of Bergami et al (US 4871689 A, as cited in the IDS dated 07/24/2024, hereafter Bergami).
Regarding claim 9, Chen in view of Seah teaches: The IC of claim 1.
Chen in view of Seah does not explicitly teach: wherein the insulating layer has a refractive index ranging from approximately 1.6 to approximately 1.9 ((as best understood to mean “a refractive index ranging from
Bergami, in the same field of endeavor of semiconductor device manufacturing, teaches: an insulating layer (Bergami 52, col 8, lines 13-22) has a refractive index ranging from 1.68 to 2.01 (Bergami col 10, lines 12-25, 1.68 to 2.01).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the insulating layer of Chen in view of Seah, such that it has “a refractive index ranging from 1.6 to 1.9”, as taught by Bergami, in order to provide reduced etch sensitivity to oxide-attacking etchants during subsequent processing (Bergami col 7, lines 41-50).
Allowable Subject Matter
Claims 17-26 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 17, it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
a second resist protective layer having the first thickness disposed between the CESL structure and the first resist protective layer. (Applicant fig 1, 3, ¶0019-0021, 0066-0071).
Chen et al (US 20170110467 A1, as cited in the IDS dated 11/20/2025, hereafter Chen) teaches: An integrated chip (IC)(Chen 2), comprising:
a substrate (Chen 100, ¶0038);
a floating gate electrode (Chen 14, FG, ¶0040) disposed over the substrate (Chen fig 2);
a first resist protective layer (Chen 300, ¶0045) having a first thickness disposed over the floating gate electrode (Chen fig 2, ¶0050);
a contact etch stop layer (CESL) structure (Chen 312) disposed over the floating gate electrode (Chen fig 2, ¶0050).
Seah et al (US 6689653 B1, as cited in the IDS dated 07/24/2024, hereafter Seah) teaches: a second resist protective layer (Seah 10); a first resist protective layer (Seah 8); and
an insulating layer (Seah 9b) separating the first resist protective layer from the second resist protective layer (Seah fig 3).
Therefore, Chen in view of Seah in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Chen, Seah, Li, Bu, Bergami, or any other prior arts of record so that all of limitations of claim 17 as a whole can be met.
Regarding claims 18-20, the dependent claims are allowed for their dependency to claim 17.
Regarding claim 21, it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in
a second resist protective layer disposed directly over the first, inner portion of the first resist protective layer, and having outermost sidewalls that are spaced apart by a second distance, the second distance being less than the first distance. (Applicant fig 3, ¶0049).
Chen et al (US 20170110467 A1, as cited in the IDS dated 11/20/2025, hereafter Chen) teaches: A device (Chen 2), comprising: a substrate (Chen 100, ¶0038);
a floating gate electrode (Chen 14, FG, ¶0040) over the substrate (Chen fig 2);
a first resist protective layer (Chen 300, ¶0045) having a first, inner portion directly over the floating gate electrode and a second, outer portion that extends down from the first, inner portion and has outermost sidewalls that are spaced apart by a first distance (Chen fig 2).
Seah et al (US 6689653 B1, as cited in the IDS dated 07/24/2024, hereafter Seah) teaches: a second resist protective layer (Seah 10) disposed directly over a first resist protective layer (Seah 8)(Seah fig 3); and
an insulating layer (Seah 9b) separating the first resist protective layer from the second resist protective layer (Seah fig 3).
Therefore, Chen in view of Seah in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Chen, Seah, Li, Bu, Bergami, or any other prior arts of record so that all of limitations of claim 21 as a whole can be met.
Regarding claims 22-26, the dependent claims are allowed for their dependency to claim 21.
Conclusion
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818
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