DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shao et al. (US 2023/0015279 A1 hereinafter referred to as “Shao”).
With respect to claim 1, Chao discloses, in Figs.1-6, a method of manufacturing a semiconductor device, the method comprising: forming a memory stack (20) comprising alternating layers of a plurality of silicon (Si) layers (203) and a plurality of silicon germanium (SiGe) layers (202) on a substrate, the memory stack including a word line contact region/(region along b-be’) and a memory array region/(region along a-ae’) having a plurality of memory units (see step Figs.2A-2C, Par.[0039]-[0041] wherein when the substrate 201 is a silicon substrate, the material of the semiconductor layer 203 is silicon, a material of the sacrificial layer 202 is silicon germanium, and the stacked structure 20 is composed of a silicon/silicon germanium/silicon/silicon germanium superlattice structure; see Par.[0060] wherein the number of stacked layers of the semiconductor device provided by the embodiments of the present disclosure is not limited, so that the DRAM Logic can realize 3D development like a computer flash memory device (NAND)); selectively etching the plurality of silicon germanium (SiGe) layers (202) in both the word line contact region (b-be’) and the memory array region (a-ae’) to form a first opening (207) (see Par.[0047] wherein as shown in FIG. 2D, a dry etching process or a wet etching process may be employed to remove the sacrificial layers 202 in the semiconductor pillars 205; after the sacrificial layers 202 are removed, the second grooves 207 are formed at locations of the original sacrificial layers 202); depositing a nitride material (208’) on the plurality of silicon (Si) layers (203) to form a plurality of nitride layers (208’) in both the word line contact region (b-be’) and the memory array region (a-ae’); and depositing and oxide material (209’) on the plurality of nitride layers (208’) to form a plurality of oxide layers (209’) in both the word line contact region (b-be’) and the memory array region (a-ae’) (see Par.[0049]-[0050] wherein the initial gate oxide layer 208′ may be formed from a material, such as silicon dioxide or silicon oxynitride; the initial dielectric layer 209′ may be a high-K dielectric layer; the initial dielectric layer 209′ may be a metal silicate or a metal oxide, for example, one or more of tantalum oxide (Ta.sub.2O.sub.5), titanium oxide (TiO.sub.2), zirconia (ZrO.sub.2), alumina (Al.sub.2O.sub.3) Hafnium silicon oxide (HfSiO.sub.2) or hafnium oxide (HfO2) and other materials).
With respect to claim 2, Chao discloses, in Figs.1-6, the method, further comprising recessing the plurality of nitride layers (208’) to form a plurality of second openings in both the word line contact region (b-be’) and the memory array region (a-ae’) (see Par.[0055] wherein as shown in FIG. 2G, after the word line pillars 206 are formed, the initial gate oxide layer 208′ and the initial dielectric layer 209′ except in the word line pillars 206 are to be removed to form the gate oxide layers 208 and the dielectric layers 209 in the word line pillars 206).
With respect to claim 3, Chao discloses, in Figs.1-6, the method, further comprising depositing a word line metal (206) in the plurality of second openings simultaneously in both the word line contact region (b-be’) and the memory array region (a-ae’) (see Par.[0055] wherein as shown in FIG. 2G, after the word line pillars 206 are formed, the initial gate oxide layer 208′ and the initial dielectric layer 209′ except in the word line pillars 206 are to be removed to form the gate oxide layers 208 and the dielectric layers 209 in the word line pillars 206).
With respect to claim 4, Chao discloses, in Figs.1-6, the method, further comprising, prior to depositing the nitride material, trimming the plurality of silicon (Si) layers to form a plurality of trimmed silicon (Si) layers (203) (see step of Fig.2E wherein Si layers are thinner at least in region b-be’).
With respect to claim 5, Chao discloses, in Figs.1-6, the method, wherein the nitride material comprises silicon nitride (SiN) and wherein the oxide material comprises silicon oxide (SiOx) (see Par.[0049]-[0050] wherein the initial gate oxide layer 208′ may be formed from a material, such as silicon dioxide or silicon oxynitride (i.e.; SiON comprises SiN); the initial dielectric layer 209′ may be a high-K dielectric layer; the initial dielectric layer 209′ may be a metal silicate or a metal oxide, for example, one or more of tantalum oxide (Ta.sub.2O.sub.5), titanium oxide (TiO.sub.2), zirconia (ZrO.sub.2), alumina (Al.sub.2O.sub.3) Hafnium silicon oxide (HfSiO.sub.2 (i.e.; HfSiO2 comprises SiO2)) or hafnium oxide (HfO2) and other materials).
With respect to claim 6, Chao discloses, in Figs.1-6, the method, wherein trimming the plurality of silicon (Si) layers comprises decreasing a thickness of each of the plurality of silicon (Si) layers from a first thickness to a second thickness (see step of Fig.2E wherein Si layers are thinner at least in region b-be’).
Claims 1-11, 13-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoon et al. (US 2023/0269928 A1 hereinafter referred to as “Yoon”).
With respect to claim 1, Yoon discloses, in Figs.22-33, a method of manufacturing a semiconductor device, the method comprising: forming a memory stack comprising alternating layers of a plurality of silicon (Si) layers (14, 16) and a plurality of silicon germanium (SiGe) layers (13, 15) on a substrate (11), the memory stack including a word line contact region (CAR) and a memory array region (CTR) having a plurality of memory units (see Par.[0074] wherein the first and second semiconductor layers 14 and 16 may include a first semiconductor material which is selected among monocrystalline silicon and monocrystalline silicon germanium, and the first and second sacrificial semiconductor layers 13 and 15 may include a second semiconductor material which is different from the first semiconductor material; for example, each of the first and second semiconductor layers 14 and 16 may be a monocrystalline silicon layer, and each of the first sacrificial semiconductor layers 13, the second sacrificial semiconductor layers 15, and the uppermost sacrificial semiconductor layer 17 may be a monocrystalline silicon germanium layer; see Par.[0103]-[0104] wherein referring to FIG. 22, the semiconductor device 200 may include a cell array portion CAR and a contact portion CTR); selectively etching the plurality of silicon germanium (SiGe) layers (13, 15) in both the word line contact region (CTR) and the memory array region (CAR) to form a first opening (AG’) (see step of Figs.26-27, Par.[0124]-[0125] wherein the first and second sacrificial semiconductor layers 13 and 15 and the uppermost sacrificial semiconductor layer 17 of the steps ST may be selectively removed through the slit SL to form initial lateral recesses AG′; the initial lateral recesses AG′ may be disposed between the first semiconductor layer 14 and the second semiconductor layer 16; the uppermost initial lateral recess AG′ of the initial lateral recesses AG′ may be disposed between the uppermost second semiconductor layer 16 and the dielectric layer 18; referring to FIG. 27, the first and second semiconductor layers 14 and 16 may be recessed through the initial lateral recesses AG′; in order to recess the first and second semiconductor layers 14 and 16, the first and second semiconductor layers 14 and 16 may be partially etched by a wet etching process or a dry etching process; the second semiconductor layers 16 may be partially etched until the first semiconductor layers 14 are removed; as a result, all of the first semiconductor layers 14 may be removed, and the second semiconductor layers 16 may become thin as represented by a reference numeral ‘16S’; the thin second semiconductor layers 16S may be simply referred to as a thin-body active layer 16S); depositing a nitride material on the plurality of silicon (Si) layers (16S) to form a plurality of nitride layers in both the word line contact region and the memory array region; and depositing and oxide material on the plurality of nitride layers (21) to form a plurality of oxide layers (22) in both the word line contact region (CTR) and the memory array region (CAR) (see step of Fig Par.[0083] wherein the sacrificial dielectric layers 21 may include silicon nitride, and the cell isolation dielectric layers 22 may include silicon oxide).
With respect to claim 2, Yoon discloses, in Figs.22-33, the method, further comprising recessing the plurality of nitride layers (21) to form a plurality of second openings (23) in both the word line contact region (CTR) and the memory array region (CAR) (see Par.[0129] wherein referring to FIG. 29, word line recesses 23 may be formed; portions of the sacrificial dielectric layers 21 may be selectively etched to form the word line recesses 23; a dummy word line recess 23D may be formed between the lower structure 11 and the lowermost-level cell isolation dielectric layer 22).
With respect to claim 3, Yoon discloses, in Figs.22-33, the method, further comprising depositing a word line metal (WL1, WL2) in the plurality of second openings (23) simultaneously in both the word line contact region (CTR) and the memory array region (CAR) (see Par.[0138] wherein contact plugs 35 penetrating the contact-level dielectric layer 34 and/or the inter-layer dielectric layer ILD may be formed; the contact plugs 35 may be coupled to each of the first word lines WL1; the contact plugs 35 may be electrically connected to the first word lines WL1; the first word lines WL1 and the second word lines WL2 may form electrically connected pairs by corresponding word line pads 32).
With respect to claim 4, Yoon discloses, in Figs.22-33, the method, further comprising, prior to depositing the nitride material, trimming the plurality of silicon (Si) layers to form a plurality of trimmed silicon (Si) layers (see step of Figs.26-27, Par.[0124]-[0125] wherein the first and second sacrificial semiconductor layers 13 and 15 and the uppermost sacrificial semiconductor layer 17 of the steps ST may be selectively removed through the slit SL to form initial lateral recesses AG′; the initial lateral recesses AG′ may be disposed between the first semiconductor layer 14 and the second semiconductor layer 16; the uppermost initial lateral recess AG′ of the initial lateral recesses AG′ may be disposed between the uppermost second semiconductor layer 16 and the dielectric layer 18; referring to FIG. 27, the first and second semiconductor layers 14 and 16 may be recessed through the initial lateral recesses AG′; in order to recess the first and second semiconductor layers 14 and 16, the first and second semiconductor layers 14 and 16 may be partially etched by a wet etching process or a dry etching process; the second semiconductor layers 16 may be partially etched until the first semiconductor layers 14 are removed; as a result, all of the first semiconductor layers 14 may be removed, and the second semiconductor layers 16 may become thin as represented by a reference numeral ‘16S’; the thin second semiconductor layers 16S may be simply referred to as a thin-body active layer 16S).
With respect to claim 5, Yoon discloses, in Figs.22-33, the method, wherein the nitride material comprises silicon nitride (SiN) and wherein the oxide material comprises silicon oxide (SiOx) (see step of Fig Par.[0083] wherein the sacrificial dielectric layers 21 may include silicon nitride, and the cell isolation dielectric layers 22 may include silicon oxide).
With respect to claim 6, Yoon discloses, in Figs.22-33, the method, wherein trimming the plurality of silicon (Si) layers comprises decreasing a thickness of each of the plurality of silicon (Si) layers from a first thickness to a second thickness (see step of Figs.26-27, Par.[0124]-[0125] wherein the first and second sacrificial semiconductor layers 13 and 15 and the uppermost sacrificial semiconductor layer 17 of the steps ST may be selectively removed through the slit SL to form initial lateral recesses AG′; the initial lateral recesses AG′ may be disposed between the first semiconductor layer 14 and the second semiconductor layer 16; the uppermost initial lateral recess AG′ of the initial lateral recesses AG′ may be disposed between the uppermost second semiconductor layer 16 and the dielectric layer 18; referring to FIG. 27, the first and second semiconductor layers 14 and 16 may be recessed through the initial lateral recesses AG′; in order to recess the first and second semiconductor layers 14 and 16, the first and second semiconductor layers 14 and 16 may be partially etched by a wet etching process or a dry etching process; the second semiconductor layers 16 may be partially etched until the first semiconductor layers 14 are removed; as a result, all of the first semiconductor layers 14 may be removed, and the second semiconductor layers 16 may become thin as represented by a reference numeral ‘16S’; the thin second semiconductor layers 16S may be simply referred to as a thin-body active layer 16S).
With respect to claim 7, Yoon discloses, in Figs.22-33, the method, wherein the first thickness is in a range of from 40 nm to 100 nm (see Par.[0112], [0114] wherein the second semiconductor layers 16 may be approximately 2 to 3 times thicker than the first semiconductor layers 14; for example, the first semiconductor layers 14 may have a thickness of approximately 20 nm, and the second semiconductor layers 16 may have a thickness of approximately 40 nm; the first semiconductor layers 14 may be approximately 2 to 3 times thicker than the second semiconductor layers 16; for example, the first semiconductor layers 14 may have a thickness of approximately 40 nm, and the second semiconductor layers 16 may have a thickness of approximately 20 nm).
With respect to claim 8, Yoon discloses, in Figs.22-33, the method, wherein the second thickness (thickness of 16S < thickness of 14, 16) is in a range of from 10 nm to 40 nm (see Par.[0112], [0114] wherein the second semiconductor layers 16 may be approximately 2 to 3 times thicker than the first semiconductor layers 14; for example, the first semiconductor layers 14 may have a thickness of approximately 20 nm, and the second semiconductor layers 16 may have a thickness of approximately 40 nm; the first semiconductor layers 14 may be approximately 2 to 3 times thicker than the second semiconductor layers 16; for example, the first semiconductor layers 14 may have a thickness of approximately 40 nm, and the second semiconductor layers 16 may have a thickness of approximately 20 nm).
With respect to claim 9, Yoon discloses, in Figs.22-33, the method, wherein the word line metal comprises one or more of a metal, a metal nitride, a conductive metal compound, and a semiconductor material (see Par.[0138] wherein contact plugs 35 penetrating the contact-level dielectric layer 34 and/or the inter-layer dielectric layer ILD may be formed; the contact plugs 35 may be coupled to each of the first word lines WL1; the contact plugs 35 may be electrically connected to the first word lines WL1; the first word lines WL1 and the second word lines WL2 may form electrically connected pairs by corresponding word line pads 32).
With respect to claim 10, Yoon discloses, in Figs.22-33, the method, wherein the metal is selected from one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), or titanium (Ti) (see Par.[0132], [0135] wherein the step of forming the first word line WL1 and the second word line WL2 may include conformally depositing titanium nitride, depositing tungsten to fill the word line recesses 23 over the titanium nitride, and etching back the titanium nitride and tungsten).
With respect to claim 11, Yoon discloses, in Figs.22-33, the method, wherein the metal nitride is selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), and zirconium nitride (ZrN) (see Par.[0132], [0135] wherein the step of forming the first word line WL1 and the second word line WL2 may include conformally depositing titanium nitride, depositing tungsten to fill the word line recesses 23 over the titanium nitride, and etching back the titanium nitride and tungsten).
With respect to claim 13, Yoon discloses, in Figs.22-33, the method, wherein the semiconductor material is selected from one or more of silicon (Si), silicon germanium (SiGe), and germanium (Ge) (see Par.[0074] wherein the first and second semiconductor layers 14 and 16 may include a first semiconductor material which is selected among monocrystalline silicon and monocrystalline silicon germanium, and the first and second sacrificial semiconductor layers 13 and 15 may include a second semiconductor material which is different from the first semiconductor material; for example, each of the first and second semiconductor layers 14 and 16 may be a monocrystalline silicon layer, and each of the first sacrificial semiconductor layers 13, the second sacrificial semiconductor layers 15, and the uppermost sacrificial semiconductor layer 17 may be a monocrystalline silicon germanium layer; see Par.[0103]-[0104] wherein referring to FIG. 22, the semiconductor device 200 may include a cell array portion CAR and a contact portion CTR).
With respect to claim 14, Yoon discloses, in Figs.22-33, a method of manufacturing a semiconductor device, the method comprising: selectively etching a plurality of silicon germanium (SiGe) layers (13, 15) in both a word line contact region (CTR) and a memory array region (CAR) of a memory stack on a substrate (11) to form a plurality of first openings (AG’) adjacent a plurality of silicon (Si) layers (14, 16) (see Par.[0074] wherein the first and second semiconductor layers 14 and 16 may include a first semiconductor material which is selected among monocrystalline silicon and monocrystalline silicon germanium, and the first and second sacrificial semiconductor layers 13 and 15 may include a second semiconductor material which is different from the first semiconductor material; for example, each of the first and second semiconductor layers 14 and 16 may be a monocrystalline silicon layer, and each of the first sacrificial semiconductor layers 13, the second sacrificial semiconductor layers 15, and the uppermost sacrificial semiconductor layer 17 may be a monocrystalline silicon germanium layer; see Par.[0103]-[0104] wherein referring to FIG. 22, the semiconductor device 200 may include a cell array portion CAR and a contact portion CTR; see step of Figs.26-27, Par.[0124]-[0125] wherein the first and second sacrificial semiconductor layers 13 and 15 and the uppermost sacrificial semiconductor layer 17 of the steps ST may be selectively removed through the slit SL to form initial lateral recesses AG′; the initial lateral recesses AG′ may be disposed between the first semiconductor layer 14 and the second semiconductor layer 16; the uppermost initial lateral recess AG′ of the initial lateral recesses AG′ may be disposed between the uppermost second semiconductor layer 16 and the dielectric layer 18; referring to FIG. 27, the first and second semiconductor layers 14 and 16 may be recessed through the initial lateral recesses AG′; in order to recess the first and second semiconductor layers 14 and 16, the first and second semiconductor layers 14 and 16 may be partially etched by a wet etching process or a dry etching process; the second semiconductor layers 16 may be partially etched until the first semiconductor layers 14 are removed; as a result, all of the first semiconductor layers 14 may be removed, and the second semiconductor layers 16 may become thin as represented by a reference numeral ‘16S’; the thin second semiconductor layers 16S may be simply referred to as a thin-body active layer 16S); depositing a nitride material (21) on the plurality of silicon (Si) layers (14, 16) to form a plurality of nitride layers (21) in both the word line contact region (CTR) and the memory array region (CAR); and depositing an oxide material on the plurality of nitride layers (21) to form a plurality of oxide layers (22) in both the word line contact region (CTR) and the memory array region (CAR) (see step of Fig Par.[0083] wherein the sacrificial dielectric layers 21 may include silicon nitride, and the cell isolation dielectric layers 22 may include silicon oxide).
With respect to claim 15, Yoon discloses, in Figs.22-33, the method, wherein the memory stack comprises alternating layers of the plurality of silicon (Si) layers and the plurality of silicon germanium (SiGe) layers (see Par.[0074] wherein the first and second semiconductor layers 14 and 16 may include a first semiconductor material which is selected among monocrystalline silicon and monocrystalline silicon germanium, and the first and second sacrificial semiconductor layers 13 and 15 may include a second semiconductor material which is different from the first semiconductor material; for example, each of the first and second semiconductor layers 14 and 16 may be a monocrystalline silicon layer, and each of the first sacrificial semiconductor layers 13, the second sacrificial semiconductor layers 15, and the uppermost sacrificial semiconductor layer 17 may be a monocrystalline silicon germanium layer; see Par.[0103]-[0104] wherein referring to FIG. 22, the semiconductor device 200 may include a cell array portion CAR and a contact portion CTR).
With respect to claim 16, Yoon discloses, in Figs.22-33, the method, further comprising, prior to depositing the nitride material, trimming the plurality of silicon (Si) layers (14, 16) to form a plurality of trimmed silicon (Si) layers (16S) (see step of Figs.26-27, Par.[0124]-[0125] wherein the first and second sacrificial semiconductor layers 13 and 15 and the uppermost sacrificial semiconductor layer 17 of the steps ST may be selectively removed through the slit SL to form initial lateral recesses AG′; the initial lateral recesses AG′ may be disposed between the first semiconductor layer 14 and the second semiconductor layer 16; the uppermost initial lateral recess AG′ of the initial lateral recesses AG′ may be disposed between the uppermost second semiconductor layer 16 and the dielectric layer 18; referring to FIG. 27, the first and second semiconductor layers 14 and 16 may be recessed through the initial lateral recesses AG′; in order to recess the first and second semiconductor layers 14 and 16, the first and second semiconductor layers 14 and 16 may be partially etched by a wet etching process or a dry etching process; the second semiconductor layers 16 may be partially etched until the first semiconductor layers 14 are removed; as a result, all of the first semiconductor layers 14 may be removed, and the second semiconductor layers 16 may become thin as represented by a reference numeral ‘16S’; the thin second semiconductor layers 16S may be simply referred to as a thin-body active layer 16S).
With respect to claim 17, Yoon discloses, in Figs.22-33, the method, wherein trimming the plurality of silicon (Si) layers comprises decreasing a thickness of each of the plurality of silicon (Si) layers from a first thickness to a second thickness decreasing a thickness of each of the plurality of silicon (Si) layers from a first thickness to a second thickness, the first thickness is in a range of from 40 nm to 100 nm and the second thickness is in a range of from 10 nm to 40 nm (see Par.[0112], [0114] wherein the second semiconductor layers 16 may be approximately 2 to 3 times thicker than the first semiconductor layers 14; for example, the first semiconductor layers 14 may have a thickness of approximately 20 nm, and the second semiconductor layers 16 may have a thickness of approximately 40 nm; the first semiconductor layers 14 may be approximately 2 to 3 times thicker than the second semiconductor layers 16; for example, the first semiconductor layers 14 may have a thickness of approximately 40 nm, and the second semiconductor layers 16 may have a thickness of approximately 20 nm).
With respect to claim 18, Yoon discloses, in Figs.22-33, the method, further comprising recessing the plurality of nitride layers to form a plurality of second openings (23) in both the word line (WL) contact region and the memory array region (CAR) (see Par.[0129] wherein referring to FIG. 29, word line recesses 23 may be formed; portions of the sacrificial dielectric layers 21 may be selectively etched to form the word line recesses 23; a dummy word line recess 23D may be formed between the lower structure 11 and the lowermost-level cell isolation dielectric layer 22).
With respect to claim 19, Yoon discloses, in Figs.22-33, the method, further comprising depositing a word line (WL1, WL2) metal in the plurality of second openings simultaneously in both the word line contact region and the memory array region (see Par.[0138] wherein contact plugs 35 penetrating the contact-level dielectric layer 34 and/or the inter-layer dielectric layer ILD may be formed; the contact plugs 35 may be coupled to each of the first word lines WL1; the contact plugs 35 may be electrically connected to the first word lines WL1; the first word lines WL1 and the second word lines WL2 may form electrically connected pairs by corresponding word line pads 32).
With respect to claim 20, Yoon discloses, in Figs.22-33, the method, wherein the word line metal comprises one or more of a metal, a metal nitride, a conductive metal compound, and a semiconductor material (see Par.[0132], [0135] wherein the step of forming the first word line WL1 and the second word line WL2 may include conformally depositing titanium nitride, depositing tungsten to fill the word line recesses 23 over the titanium nitride, and etching back the titanium nitride and tungsten).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yoon in view of Kim (US 2019/0393270 A1).
With respect to claim 12, Yoon discloses all the claimed limitations of claim 9. However, Yoon does not explicitly disclose the limitations of claim 12.
Kim discloses, in Figs.1-12, the method, wherein the conductive metal compound is selected from one or more of tungsten oxide (WOx), ruthenium oxide (RuOx), and iridium oxide (IrOx) (see Par.[0059] wherein the word lines 30 may include one of: a metal such as tungsten (W), ruthenium (Ru), copper (Cu) or aluminum (Al); a metal compound such as tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN) or ruthenium oxide (RuO.sub.2); a metal silicide such as tungsten silicide (WSi), titanium silicide (TiSi), nickel silicide (NiSi) or cobalt silicide (CoSi); or an ion doped silicon).
Yoon and Kim are analogous art because they are all directed to a memory device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Yoon to include Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify WL material in Yoon by including WL with tungsten nitride (WN), tantalum nitride (TaN) or ruthenium oxide (RuO.sub.2) matrial as taught by Kim in order to utilize its high electrical conductivity and exceptional catalytic activity that exhibit excellent stability in acidic environments and can withstand harsh chemical conditions as well as demonstrates a high melting point, and it retains its structure even under high temperatures.
Citation of Pertinent Prior Art
The prior art made of record (e.g., see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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